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241 Commits

Author SHA1 Message Date
Akira Hatanaka
8573d26722 Make FGR64RegisterClass available if target is Mips64. 
llvm-svn: 140397
 2011-09-23 18:28:39 +00:00
Akira Hatanaka
f213002a1c Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363
 2011-09-23 00:58:33 +00:00
Akira Hatanaka
60cd2b0c2f Remove unnecessary condition check. 
llvm-svn: 140291
 2011-09-22 02:41:29 +00:00
Akira Hatanaka
eb3e16d39f Change the names of functions isMips* to hasMips*. 
llvm-svn: 140214
 2011-09-20 23:53:09 +00:00
Akira Hatanaka
6731be3175 Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046
 2011-09-19 20:26:02 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Eli Friedman
6d27cb5e01 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Akira Hatanaka
02cff5ae2d Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.

llvm-svn: 138132
 2011-08-19 22:59:00 +00:00
Akira Hatanaka
163382894e Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka
1876aadea7 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.

llvm-svn: 137975
 2011-08-18 20:07:42 +00:00
Akira Hatanaka
0af1edcce0 Changed definition of EXT and INS per Bruno's comments. 
llvm-svn: 137892
 2011-08-17 22:59:46 +00:00
Akira Hatanaka
6eb513003d Add support for half-word unaligned loads and stores. 
llvm-svn: 137848
 2011-08-17 18:49:18 +00:00
Akira Hatanaka
60ccc76576 Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
llvm-svn: 137831
 2011-08-17 17:45:08 +00:00
Akira Hatanaka
0179c7fa68 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Eli Friedman
afd08dcc2c New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. 
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
 2011-08-03 21:06:02 +00:00
Eli Friedman
842ea169de Code generation for 'fence' instruction. 
llvm-svn: 136283
 2011-07-27 22:21:52 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Akira Hatanaka
cccc5fca34 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
b4db39fa83 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Akira Hatanaka
19c16a84ff Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Akira Hatanaka
ad3687eb3a Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
55b8d79a52 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Akira Hatanaka
52263f51f1 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
79f38f0ae7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Akira Hatanaka
d5690b20d3 Change destination register operands of SC instructions so that unique 
virtual registers are used. 

llvm-svn: 135403
 2011-07-18 17:44:27 +00:00
Chris Lattner
e1fe7061ce land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Cameron Zwarich
c23366d357 Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
 2011-07-08 21:39:21 +00:00
Akira Hatanaka
90fcf55a54 Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Akira Hatanaka
d3c031eb00 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Eric Christopher
f04ac137f3 Update comment for getRegForInlineAsmConstraint for Mips. 
llvm-svn: 134087
 2011-06-29 19:33:04 +00:00
Eric Christopher
82c3bcfb14 Remove getRegClassForInlineAsmConstraint for Mips. 
Part of rdar://9643582

llvm-svn: 134084
 2011-06-29 19:04:31 +00:00
Akira Hatanaka
539ba34c25 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka
1197db1f9b Coding style fixes. 
llvm-svn: 133496
 2011-06-21 01:02:03 +00:00
Akira Hatanaka
1e08980a21 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Bruno Cardoso Lopes
762b3d1f0f Silence warnings in non assert builds. Patch by David Blaikie 
llvm-svn: 133118
 2011-06-16 00:40:02 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka
ea8ce56dbb Reorganize code in MipsTargetLowering::LowerCall to improve readability. 
llvm-svn: 132756
 2011-06-08 17:39:33 +00:00
Akira Hatanaka
101d50423a Refactor MipsTargetLowering::EmitInstrWithCustomInserter. 
llvm-svn: 132726
 2011-06-07 19:28:39 +00:00
Akira Hatanaka
3b7982650c Coding style fixes. 
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
 2011-06-07 18:58:42 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes
9231127d37 Fix uninitialized variables and silence warnings 
llvm-svn: 132355
 2011-05-31 20:25:26 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00