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85b2dc0c4e
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205 Commits

Author SHA1 Message Date
Nate Begeman
85b2dc0c4e bswap implementation 
llvm-svn: 25312
 2006-01-14 03:14:10 +00:00
Evan Cheng
d92410b194 A typo. 
llvm-svn: 25307
 2006-01-14 01:18:49 +00:00
Evan Cheng
4d9bab5789 Add truncstore i1 patterns. 
llvm-svn: 25296
 2006-01-13 21:45:19 +00:00
Evan Cheng
794a7cf6fe Fix sint_to_fp (fild*) support. 
llvm-svn: 25257
 2006-01-12 22:54:21 +00:00
Evan Cheng
169206c67f Specify transformation from GlobalAddress to TargetGlobalAddress and 
ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25253
 2006-01-12 19:36:31 +00:00
Evan Cheng
978f5581c4 X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be 
linked together).

llvm-svn: 25247
 2006-01-12 08:27:59 +00:00
Evan Cheng
dd45d29b56 * Materialize GlobalAddress and ExternalSym with MOV32ri rather than 
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246
 2006-01-12 07:56:47 +00:00
Evan Cheng
5841005bdf Added ROTL and ROTR. 
llvm-svn: 25232
 2006-01-11 23:20:05 +00:00
Evan Cheng
66540aa32c Support for MEMCPY and MEMSET. 
llvm-svn: 25226
 2006-01-11 22:15:48 +00:00
Evan Cheng
e42281bcba * Add special entry code main() (to set x87 to 64-bit precision). 
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207
 2006-01-11 06:09:51 +00:00
Evan Cheng
9adc8e5a3d SSE cmov support. 
llvm-svn: 25190
 2006-01-11 00:33:36 +00:00
Evan Cheng
0cb5e32cda * fp to sint patterns. 
* fiadd, fisub, etc.

llvm-svn: 25189
 2006-01-10 22:22:02 +00:00
Evan Cheng
8504673bb2 FP_TO_INT*_IN_MEM and x87 FP Select support. 
llvm-svn: 25188
 2006-01-10 20:26:56 +00:00
Evan Cheng
154cef5ccb * Added undef patterns. 
* Some reorg.

llvm-svn: 25163
 2006-01-09 23:10:28 +00:00
Evan Cheng
d3babfe458 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. 
llvm-svn: 25158
 2006-01-09 18:33:28 +00:00
Evan Cheng
66355df170 Addd (shl x, 1) ==> (shl x, x) peepholes. 
llvm-svn: 25123
 2006-01-06 02:31:59 +00:00
Evan Cheng
1e0d7b98f3 * Fast call support. 
* FP cmp, setcc, etc.

llvm-svn: 25117
 2006-01-06 00:43:03 +00:00
Evan Cheng
6c86cf3a5f Added ConstantFP patterns. 
llvm-svn: 25108
 2006-01-05 02:08:37 +00:00
Evan Cheng
2329411038 DAG based isel call support. 
llvm-svn: 25103
 2006-01-05 00:27:02 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng
d87688fe72 * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng
995503fc91 More X86 floating point patterns. 
llvm-svn: 24990
 2005-12-23 07:31:11 +00:00
Evan Cheng
e458553c73 Bye bye HACKTROCITY. 
llvm-svn: 24935
 2005-12-22 02:26:21 +00:00
Evan Cheng
fb6413e05a * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Evan Cheng
add305de26 Oops. Accidentally deleted RET pattern. It's still needed for return void; 
llvm-svn: 24920
 2005-12-21 22:22:16 +00:00
Evan Cheng
6f15189a77 * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
 2005-12-21 20:21:51 +00:00
Chris Lattner
347c6eedae This was meant to go in 
llvm-svn: 24900
 2005-12-21 07:50:26 +00:00
Chris Lattner
884def40f4 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns 
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
 2005-12-21 07:47:04 +00:00
Chris Lattner
ee15b5393f Wrap some long lines: no functionality change 
llvm-svn: 24898
 2005-12-21 05:34:58 +00:00
Evan Cheng
0226113ed5 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng
ace8f1fafa SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. 
llvm-svn: 24886
 2005-12-20 22:59:51 +00:00
Evan Cheng
1c3ea75ffc Added X86 readport patterns. 
llvm-svn: 24879
 2005-12-20 07:38:38 +00:00
Evan Cheng
bb34a50cb0 X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Chris Lattner
399dfec939 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Evan Cheng
6a94c77c55 Added anyext, modelled as zext on X86. 
llvm-svn: 24759
 2005-12-17 01:47:57 +00:00
Evan Cheng
5d90b26707 Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng
43152cb8b6 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Evan Cheng
f72e7055c0 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng
576b826f71 Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Evan Cheng
3b094e89fb Added sext and zext patterns. 
llvm-svn: 24705
 2005-12-14 02:22:27 +00:00
Evan Cheng
ad1e2fd14a Add load + store folding srl and sra patterns. 
llvm-svn: 24696
 2005-12-13 07:24:22 +00:00
Evan Cheng
63f60d3edb Beautify a few patterns. 
llvm-svn: 24690
 2005-12-13 02:40:18 +00:00
Evan Cheng
95d46be9e6 Some shl patterns which do load + store folding. 
llvm-svn: 24689
 2005-12-13 02:34:51 +00:00
Evan Cheng
6beadf1c29 A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
llvm-svn: 24688
 2005-12-13 01:57:51 +00:00
Evan Cheng
d233c28d29 Add and, or, and xor patterns which fold load + stores. 
llvm-svn: 24687
 2005-12-13 01:41:36 +00:00
Evan Cheng
62999d6c5d Add inc + dec patterns which fold load + stores. 
llvm-svn: 24686
 2005-12-13 01:02:47 +00:00
Evan Cheng
7f9fb7b095 Add neg and not patterns which fold load + stores. 
llvm-svn: 24685
 2005-12-13 00:54:44 +00:00
Evan Cheng
240071c011 Missed a couple redundant explicit type casts. 
llvm-svn: 24684
 2005-12-13 00:25:07 +00:00
Evan Cheng
e80ec06aaf Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
llvm-svn: 24683
 2005-12-13 00:14:11 +00:00
Evan Cheng
ea7f208813 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. 
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682
 2005-12-13 00:01:09 +00:00