Craig Topper
ac623f26d9
Add neverHasSideEffects=1 on a couple move instructions.
...
llvm-svn: 190259
2013-09-08 00:50:45 +00:00
Elena Demikhovsky
2f3377ea54
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS
...
llvm-svn: 189472
2013-08-28 11:21:58 +00:00
Elena Demikhovsky
471e732613
AVX-512: added conversion instructions.
...
llvm-svn: 189349
2013-08-27 13:54:04 +00:00
Elena Demikhovsky
4333460954
AVX-512: Added shuffle instructions -
...
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
single and double forms.
llvm-svn: 189215
2013-08-26 12:45:35 +00:00
Elena Demikhovsky
f09dad5d90
AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
...
llvm-svn: 188786
2013-08-20 11:00:29 +00:00
Craig Topper
94afe57f94
Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
...
llvm-svn: 188743
2013-08-20 04:24:14 +00:00
Elena Demikhovsky
406cf0ea6d
AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.
...
llvm-svn: 188637
2013-08-18 13:08:57 +00:00
Benjamin Kramer
c63386d01a
X86: Turn fp selects into mask operations.
...
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
llvm-svn: 187706
2013-08-04 12:05:16 +00:00
Elena Demikhovsky
2f33e9fa89
AVX-512 set: added VEXTRACTPS instruction
...
llvm-svn: 187705
2013-08-04 10:46:07 +00:00
Elena Demikhovsky
175a2e60dd
Added INSERT and EXTRACT intructions from AVX-512 ISA.
...
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
llvm-svn: 187491
2013-07-31 11:35:14 +00:00
Craig Topper
45e8fdfc7f
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
...
Patch by Richard Mitton.
llvm-svn: 187476
2013-07-31 02:47:52 +00:00
Craig Topper
11e78f4bb0
Remove some errant space charcters in mnemonic strings.
...
llvm-svn: 186932
2013-07-23 06:45:34 +00:00
Craig Topper
9f41c21050
More Intel syntax alias fixes.
...
llvm-svn: 186814
2013-07-22 09:58:07 +00:00
Craig Topper
73e7313381
Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.
...
llvm-svn: 186812
2013-07-22 09:22:49 +00:00
Elena Demikhovsky
1c6fe6138b
Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
...
llvm-svn: 183626
2013-06-09 07:37:10 +00:00
Michael Liao
d464e3d65b
[PATCH] Fix VGATHER* operand constraints
...
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."
---
[1] http://software.intel.com/sites/default/files/319433-014.pdf
llvm-svn: 183327
2013-06-05 18:12:26 +00:00
Elena Demikhovsky
9523e885e5
Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD.
...
No functional changes.
llvm-svn: 182371
2013-05-21 12:04:22 +00:00
Preston Gurd
ed3b81e028
Corrected Atom latencies for SSE SQRT instructions.
...
llvm-svn: 181346
2013-05-07 19:57:34 +00:00
Rafael Espindola
056abc9e26
Put VMOVPQIto64rr in the VRPDI class.
...
Patch by Joshua Magee.
llvm-svn: 180842
2013-05-01 13:00:16 +00:00
Benjamin Kramer
11723aa321
X86: Now that we have a canonical form for vector integer abs, match it into pabs.
...
llvm-svn: 180600
2013-04-26 12:05:21 +00:00
Jakob Stoklund Olesen
b728975493
Annotate the remaining x86 instructions with SchedRW lists.
...
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.
There are still unannotated instructions remaining, but they don't have
itinerary classes either.
llvm-svn: 178051
2013-03-26 18:24:22 +00:00
Jakob Stoklund Olesen
0ac9ff5688
Remove IIC_DEFAULT from X86Schedule.td
...
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.
llvm-svn: 177937
2013-03-25 23:12:41 +00:00
Jakob Stoklund Olesen
b3af273625
Model prefetches and barriers as loads.
...
It's not yet clear if these instructions need a more careful model.
llvm-svn: 177599
2013-03-20 23:09:53 +00:00
Jakob Stoklund Olesen
042f102514
Add a catch-all WriteSystem SchedWrite type.
...
This is used for all the expensive system instructions.
llvm-svn: 177598
2013-03-20 23:09:50 +00:00
Jakob Stoklund Olesen
305e22bdab
Annotate the remaining SSE MOV instructions.
...
llvm-svn: 177592
2013-03-20 22:37:16 +00:00
Jakob Stoklund Olesen
96a403dd67
Annotate SSE horizontal and integer instructions.
...
llvm-svn: 177591
2013-03-20 22:37:13 +00:00
Jakob Stoklund Olesen
d202f35d06
Add some missing SSE annotations.
...
llvm-svn: 177540
2013-03-20 16:56:39 +00:00
Jakob Stoklund Olesen
3b039fa614
Annotate various null idioms with SchedRW lists.
...
llvm-svn: 177461
2013-03-19 23:23:31 +00:00
Jakob Stoklund Olesen
a8c3f3d12c
Annotate SSE float conversions with SchedRW lists.
...
llvm-svn: 177460
2013-03-19 23:23:29 +00:00
Jakob Stoklund Olesen
2d375df1d8
Add SchedRW annotations to most of X86InstrSSE.td.
...
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.
Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.
llvm-svn: 177326
2013-03-18 22:01:35 +00:00
Nadav Rotem
03b60b8657
Unaligned loads should use the VMOVUPS opcode.
...
llvm-svn: 177130
2013-03-14 23:49:44 +00:00
Craig Topper
97391f52d3
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
...
llvm-svn: 173667
2013-01-28 06:48:25 +00:00
Craig Topper
c5444baf77
Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together.
...
llvm-svn: 172704
2013-01-17 06:59:42 +00:00
Craig Topper
58b9662000
Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments.
...
llvm-svn: 172379
2013-01-14 07:46:34 +00:00
Craig Topper
7dac5e7e3d
Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended
...
llvm-svn: 172378
2013-01-14 07:26:58 +00:00
Benjamin Kramer
26eae94ea6
X86: Add patterns for X86ISD::VSEXT in registers.
...
Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.
llvm-svn: 172353
2013-01-13 11:37:04 +00:00
Craig Topper
b80024c8e6
Remove unnecessary # tokens at the beginning and end of defm names.
...
llvm-svn: 171694
2013-01-07 05:04:39 +00:00
Craig Topper
7af95b6c84
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
...
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
llvm-svn: 171668
2013-01-06 20:39:29 +00:00
Craig Topper
23d1063500
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
...
llvm-svn: 171356
2013-01-02 08:00:39 +00:00
Craig Topper
f7827c5751
Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW.
...
llvm-svn: 171355
2013-01-02 07:27:49 +00:00
Rafael Espindola
cd13b5a188
Revert 171351. It broke MC/X86/x86-32-avx.s.
...
llvm-svn: 171352
2013-01-02 01:35:11 +00:00
Craig Topper
334e5f128c
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
...
llvm-svn: 171351
2013-01-01 20:53:20 +00:00
Craig Topper
c4da4d53eb
Remove unused argument from a multiclass.
...
llvm-svn: 171340
2013-01-01 03:42:44 +00:00
Craig Topper
94f978e60f
Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS.
...
llvm-svn: 171339
2013-01-01 03:30:21 +00:00
Craig Topper
4cb9a8b42e
Remove 2 unused multiclasses.
...
llvm-svn: 171338
2013-01-01 02:02:45 +00:00
Craig Topper
912389c854
Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended.
...
llvm-svn: 171337
2013-01-01 00:11:07 +00:00
Craig Topper
3a64f728dc
Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.
...
llvm-svn: 171336
2012-12-31 23:49:05 +00:00
Craig Topper
175e8218c5
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
...
llvm-svn: 171237
2012-12-29 18:18:20 +00:00
Craig Topper
93fdde7fff
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
...
llvm-svn: 171227
2012-12-29 16:44:25 +00:00
Craig Topper
e2fd2d2c63
Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.
...
llvm-svn: 171171
2012-12-27 22:53:47 +00:00