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Commit Graph

816 Commits

Author SHA1 Message Date
Evan Cheng
88726d85eb Encode misc arithmetic instructions.
llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f Encode extend instructions; more clean up.
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng
078361bddc Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng
058721d10b Fix so_imm encoding bug; add support for MOVi2pieces.
llvm-svn: 58790
2008-11-06 02:25:39 +00:00
Evan Cheng
ca6759021b Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng
ce97712aa6 Encode pic load / store instructions; fix some encoding bugs.
llvm-svn: 58780
2008-11-05 23:22:34 +00:00
Evan Cheng
9970c31dcf Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Dan Gohman
cd4b68bee9 Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
2008-11-05 04:14:16 +00:00
Evan Cheng
59112bc108 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
llvm-svn: 58725
2008-11-04 22:19:55 +00:00
Evan Cheng
45496b349f Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
llvm-svn: 58714
2008-11-04 19:57:48 +00:00
Evan Cheng
d63b7563b7 Debug output tweak.
llvm-svn: 58708
2008-11-04 17:58:53 +00:00
Evan Cheng
088f7c51a4 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
llvm-svn: 58707
2008-11-04 17:57:07 +00:00
Evan Cheng
28e234a959 For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688
2008-11-04 09:30:48 +00:00
Evan Cheng
f15a9cfb31 Stylistic change.
llvm-svn: 58683
2008-11-04 06:10:06 +00:00
Evan Cheng
f117632c3f Handle ARM machine constantpool entries.
llvm-svn: 58671
2008-11-04 00:50:32 +00:00
Evan Cheng
999398c004 Remove a dead switch statement.
llvm-svn: 58644
2008-11-03 21:26:52 +00:00
Evan Cheng
b3fd30ed7c Minor code restructuring. No functionality change.
llvm-svn: 58643
2008-11-03 21:02:39 +00:00
Jim Grosbach
5262898365 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Dan Gohman
155df8a79e Refactor various TargetAsmInfo subclasses' TargetMachine members away
adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624
2008-11-03 18:22:42 +00:00
Evan Cheng
53d4b6531e Add comment.
llvm-svn: 58533
2008-10-31 19:56:03 +00:00
Evan Cheng
07f57f0e41 Use better data structure for ConstPoolId2AddrMap.
llvm-svn: 58532
2008-10-31 19:55:13 +00:00
Evan Cheng
31306c546f Actually make debug output understandable.
llvm-svn: 58529
2008-10-31 19:15:52 +00:00
Evan Cheng
6a824a7741 Forgot this in last commit.
llvm-svn: 58527
2008-10-31 19:11:09 +00:00
Evan Cheng
afe2deb372 Encode PICADD; some code clean up.
llvm-svn: 58526
2008-10-31 19:10:44 +00:00
Evan Cheng
56f4944f9a I think we got non-machine specific constpool entries covered.
llvm-svn: 58474
2008-10-30 23:43:36 +00:00
Evan Cheng
6f41528b91 ARM JIT should observe -relocation-model command line option.
llvm-svn: 58433
2008-10-30 16:10:54 +00:00
Evan Cheng
69c2588244 Correct way to handle CONSTPOOL_ENTRY instructions.
llvm-svn: 58409
2008-10-29 23:55:43 +00:00
Evan Cheng
5e8fa6ef36 Add debugging support.
llvm-svn: 58408
2008-10-29 23:55:17 +00:00
Jim Grosbach
d735f403a0 Support for constant islands in the ARM JIT.
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338
2008-10-28 18:25:49 +00:00
David Greene
93f9f0f718 Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278
2008-10-27 21:56:29 +00:00
Oscar Fuentes
51e77b801a CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.
llvm-svn: 58133
2008-10-25 03:40:32 +00:00
Jim Grosbach
a8a40398e8 remove extraneous #ifdef's
llvm-svn: 58006
2008-10-22 22:27:51 +00:00
Oscar Fuentes
a932cae97a CMake: Turned some libraries into partially linked objects. Corrected
names of LLVMCore and ARMCodeGen.

llvm-svn: 57943
2008-10-22 02:51:53 +00:00
Jim Grosbach
24a4744d53 use pre-UAL mnemonics for push/pop for compilaton callback function
llvm-svn: 57911
2008-10-21 16:54:12 +00:00
Jim Grosbach
1de8b23129 Update the stub and callback code to handle lazy compilation. The stub
is re-written by the callback to branch directly to the compiled code
in future invocations.

Added back in range-based memory permission functions for the updating of
the stub on Darwin.

llvm-svn: 57846
2008-10-20 21:39:23 +00:00
Dan Gohman
86527c1834 Const-ify several TargetInstrInfo methods.
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
Evan Cheng
3faedff2de Rename LoadX to LoadExt.
llvm-svn: 57526
2008-10-14 21:26:46 +00:00
Jim Grosbach
d0ff59ec42 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
llvm-svn: 57524
2008-10-14 20:36:24 +00:00
Dan Gohman
9543edc4ef Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521
2008-10-14 20:25:08 +00:00
Chris Lattner
7910d59d44 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
2008-10-11 22:08:30 +00:00
Jim Grosbach
974799922e Comment to be explicit that the enumeration values for CondCodes matter.
llvm-svn: 57295
2008-10-08 16:24:35 +00:00
Jim Grosbach
8ac554209f Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
llvm-svn: 57262
2008-10-07 21:08:09 +00:00
Jim Grosbach
5fb8bb7434 need ARM.h for ARMCC definition
llvm-svn: 57261
2008-10-07 21:01:51 +00:00
Jim Grosbach
d44d20be6e Encode the conditional execution predicate when JITing.
llvm-svn: 57258
2008-10-07 19:05:35 +00:00
Jim Grosbach
61f8207ac9 Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
llvm-svn: 57252
2008-10-07 17:42:09 +00:00
Jim Grosbach
a52546fec4 Fix Opcode values of CMP and CMN
llvm-svn: 57251
2008-10-07 17:40:46 +00:00
Anton Korobeynikov
1f7e8162d9 Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
llvm-svn: 57106
2008-10-05 08:53:29 +00:00
Dan Gohman
00034b1416 Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016
2008-10-03 16:55:19 +00:00