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892b99b327
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19768 Commits

Author SHA1 Message Date
Akira Hatanaka
892b99b327 64-bit arbitrary immediate pattern. 
llvm-svn: 144448
 2011-11-12 02:25:00 +00:00
Akira Hatanaka
a0188ffa09 Function for handling byval arguments. 
llvm-svn: 144447
 2011-11-12 02:20:46 +00:00
Daniel Dunbar
73d41b0f03 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

llvm-svn: 144444
 2011-11-12 02:10:57 +00:00
Jim Grosbach
7e41554aa7 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

llvm-svn: 144439
 2011-11-12 00:58:43 +00:00
Jim Grosbach
312b583950 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437
 2011-11-12 00:31:53 +00:00
Jim Grosbach
7fccd540c9 Oops. Missed the isel half of this. revert while I sort that out. 
llvm-svn: 144431
 2011-11-11 23:51:31 +00:00
Jim Grosbach
13af5276a1 ARM assembly parsing for VST1 two-register encoding. 
llvm-svn: 144430
 2011-11-11 23:45:47 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax. 
llvm-svn: 144427
 2011-11-11 23:34:43 +00:00
Chad Rosier
a2a0fbeded Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Daniel Dunbar
67b8edce31 CMake: Fix CMake build for new Mips tblgen file. 
llvm-svn: 144423
 2011-11-11 23:12:56 +00:00
Jim Grosbach
bc077320e1 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

llvm-svn: 144422
 2011-11-11 23:08:10 +00:00
Daniel Dunbar
a626481a77 Target/LLVMBuild: Order components alphabetically. 
llvm-svn: 144415
 2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
bc4e9ca90e Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
 2011-11-11 22:58:42 +00:00
Jim Grosbach
01a7117803 Nuke no longer accurate comment. 
llvm-svn: 144411
 2011-11-11 22:30:06 +00:00
Andrew Trick
6ff75a5d8d Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.

llvm-svn: 144409
 2011-11-11 22:18:09 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

llvm-svn: 144407
 2011-11-11 21:27:40 +00:00
Dan Bailey
ad6c209a79 allow non-device function calls in PTX when natively handling device-side printf 
llvm-svn: 144388
 2011-11-11 14:45:12 +00:00
Dan Bailey
6c29989135 add rules in tabgen for PTX COPY_ADDRESS of frameindex 
llvm-svn: 144387
 2011-11-11 14:45:06 +00:00
Benjamin Kramer
e5295a772e Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. 
llvm-svn: 144384
 2011-11-11 12:39:41 +00:00
Benjamin Kramer
e2cdc6f3e7 Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler. 
llvm-svn: 144383
 2011-11-11 12:39:35 +00:00
Craig Topper
50df7c3842 Add lowering for AVX2 shift instructions. 
llvm-svn: 144380
 2011-11-11 07:39:23 +00:00
Chad Rosier
98f48b009e Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08 Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Akira Hatanaka
4ff64c3ed4 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373
 2011-11-11 04:18:21 +00:00
Akira Hatanaka
3b1457c21d 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka
40d8c440ad Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
llvm-svn: 144371
 2011-11-11 04:11:56 +00:00
Akira Hatanaka
23c5cb5daf Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Akira Hatanaka
b83d016dd7 64-bit versions of jal, jalr and bal. 
llvm-svn: 144368
 2011-11-11 04:03:54 +00:00
Akira Hatanaka
5f233b2627 Emit Mips64's sequence of instructions that set global register in prologue. 
llvm-svn: 144367
 2011-11-11 04:00:29 +00:00
Akira Hatanaka
e56d824b2e Fix printing of MCSymbolRegExpr. Needs three closing parentheses for 
VK_Mips_GPOFF_HI/LO.

llvm-svn: 144366
 2011-11-11 03:58:36 +00:00
Eli Friedman
285b451941 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
llvm-svn: 144361
 2011-11-11 03:16:38 +00:00
Chad Rosier
38f07d3f9c When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Bill Wendling
3c30beb55a If we have to reset the calculation of the compact encoding, then also reset the 
"saved register" index.
<rdar://problem/10430076>

llvm-svn: 144350
 2011-11-11 00:59:14 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Daniel Dunbar
846fb32afc LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
llvm-svn: 144344
 2011-11-11 00:23:56 +00:00
Jim Grosbach
ddf85f6be2 Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

llvm-svn: 144338
 2011-11-10 23:58:34 +00:00
Jim Grosbach
d1d04109ff ARM let processInstruction() tranforms chain. 
llvm-svn: 144337
 2011-11-10 23:42:14 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach
615c824de4 Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

llvm-svn: 144329
 2011-11-10 23:01:27 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
 2011-11-10 22:10:12 +00:00
Daniel Dunbar
57e8d2b3d0 build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler 
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.

llvm-svn: 144321
 2011-11-10 22:00:37 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Jim Grosbach
614f35bb30 ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

llvm-svn: 144315
 2011-11-10 20:48:53 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Daniel Dunbar
710e8f8758 build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for 
consistency with other targets.

llvm-svn: 144292
 2011-11-10 15:35:14 +00:00
Nadav Rotem
e3d8f1a069 AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266
 2011-11-10 06:54:20 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Daniel Dunbar
138437ad27 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
f0c4aed0ab llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253
 2011-11-10 00:50:07 +00:00