Jim Grosbach
62873cae5f
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
af9cc198cf
Tidy up a bit.
...
llvm-svn: 146190
2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642
ARM VSUB implied destination operand form aliases.
...
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf
Tidy up a bit.
...
llvm-svn: 146181
2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
Jim Grosbach
e1fe053f6e
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c
Tidy up.
...
llvm-svn: 146113
2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
dd3788b044
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
Jim Grosbach
1ccae84fa7
Thumb2 alias for long-form pop and friends.
...
rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9
Tidy up. Move MachO tests to MachO directory.
...
llvm-svn: 146038
2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
ed2be25205
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
...
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
Jim Grosbach
8bdbe92631
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
...
MC/MachO assumes x86.
llvm-svn: 145916
2011-12-06 03:56:05 +00:00
Jim Grosbach
74bbb6454e
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09
Update tests for r145860. Add a few new ones.
...
llvm-svn: 145861
2011-12-05 22:21:28 +00:00
Jim Grosbach
655b017748
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
Jim Grosbach
9c017fb254
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
Jim Grosbach
6ae4df64e7
ARM tests for VLD1 single lane w/ writeback.
...
llvm-svn: 145713
2011-12-02 22:03:52 +00:00
Jim Grosbach
a568ef0db6
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach
3129a92b38
Add some tests for all-lanes VLD1 parsing.
...
llvm-svn: 145512
2011-11-30 19:37:38 +00:00
Jim Grosbach
538759efa7
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Jim Grosbach
fc7e76b194
Enable some VST1 tests and add a few more.
...
llvm-svn: 145443
2011-11-29 22:40:32 +00:00
Chris Lattner
9d1e8420ff
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
...
llvm-svn: 145171
2011-11-27 06:54:59 +00:00
Jim Grosbach
1b837af2bd
Remove obsolete test.
...
The PLD encoding is checked via the .s file now.
llvm-svn: 144853
2011-11-16 22:50:38 +00:00
Jim Grosbach
fe5f0cfa29
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach
8fae277866
Update test for r144842.
...
llvm-svn: 144851
2011-11-16 22:46:27 +00:00
Jim Grosbach
044acb8bee
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
Jim Grosbach
b8ebc386df
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
Jim Grosbach
4d0ad5a4e0
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
Jim Grosbach
8987b277cb
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
Jim Grosbach
e4933acaa7
Testcase for r144684.
...
llvm-svn: 144685
2011-11-15 19:56:17 +00:00
Jim Grosbach
df951fa128
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
Jim Grosbach
6846540505
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
Jim Grosbach
00283a5c8e
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
Jim Grosbach
4a2f107b04
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Jim Grosbach
13b7ab7527
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Jim Grosbach
1d581ecb00
ARM allow Q registers in vldm/vstm register lists.
...
rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
Jim Grosbach
bd7df609b7
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
Jim Grosbach
c3651cb620
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
Jim Grosbach
f5943e4c5e
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Jim Grosbach
8591bd2bab
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
Benjamin Kramer
89ebc7ab4b
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Jim Grosbach
f3285dba99
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
Jim Grosbach
72ab459378
Thumb2 ADD/SUB instructions encoding selection outside IT block.
...
Outside an IT block, "add r3, #2 " should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
Jim Grosbach
dac7815a91
ARM Allow 'q' registers in VLD/VST vector lists.
...
Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
Jim Grosbach
4f7964293a
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
...
rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
...
rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
Jim Grosbach
e3c6fa663f
Thumb2 ldr pc-relative encoding fixes.
...
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
Jim Grosbach
fabe0f2f0b
ARM assembly parsing and encoding for VLD1 with writeback.
...
Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
Jim Grosbach
0bb9a86fc7
Update test for r142801.
...
llvm-svn: 142806
2011-10-24 17:26:26 +00:00
Jim Grosbach
d964cf8939
Assembly parsing for 4-register sequential variant of VLD2.
...
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e
Assembly parsing for 2-register sequential variant of VLD2.
...
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95
Assembly parsing for 4-register variant of VLD1.
...
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Owen Anderson
2021ad2133
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
Owen Anderson
ffca195c01
Fix tests for corrected MSR encodings.
...
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
Jim Grosbach
e9d1df8266
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
...
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
Jim Grosbach
954465d59a
Tidy up formatting.
...
llvm-svn: 142582
2011-10-20 14:57:47 +00:00
Jim Grosbach
972f26d936
ARM VTBX (one register) assembly parsing and encoding.
...
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
Jim Grosbach
6110df7008
Tidy up formatting.
...
llvm-svn: 142422
2011-10-18 21:09:01 +00:00
Jim Grosbach
de82cec744
Tidy up formatting.
...
llvm-svn: 142421
2011-10-18 21:08:16 +00:00
Jim Grosbach
f0d2d6bfc1
Enable more encoded immediate tests.
...
llvm-svn: 142415
2011-10-18 20:20:51 +00:00
Jim Grosbach
8c1298946c
More vmov lane testcases.
...
llvm-svn: 142414
2011-10-18 20:19:48 +00:00
Jim Grosbach
ff8c26a53f
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2
ARM vmov assembly parsing for the lane index operand.
...
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
Jim Grosbach
988b8dd4ce
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
Owen Anderson
39a3d3305a
Another failing encoding.
...
llvm-svn: 142388
2011-10-18 18:23:03 +00:00
Jim Grosbach
de8f8bec78
Fix NEON mul encoding tests. Wrong file contents previously.
...
llvm-svn: 142387
2011-10-18 18:14:55 +00:00
Jim Grosbach
2752e0b869
ARM vqdmulh assembly parsing for the lane index operand.
...
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
Jim Grosbach
d2162f8c95
Remove duplicate test.
...
llvm-svn: 142383
2011-10-18 18:05:50 +00:00
Jim Grosbach
86d53ed3d4
Tidy up formatting.
...
llvm-svn: 142382
2011-10-18 18:05:16 +00:00
Jim Grosbach
b56577b650
ARM vmul assembly parsing for the lane index operand.
...
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
Jim Grosbach
93213f0ca9
Tidy up.
...
llvm-svn: 142380
2011-10-18 18:01:09 +00:00
Owen Anderson
593bfe68d2
Add a few more testcases.
...
llvm-svn: 142379
2011-10-18 17:57:31 +00:00
Owen Anderson
77f405511d
Add several FIXME cases for ARM encodings.
...
llvm-svn: 142377
2011-10-18 17:50:22 +00:00
Jim Grosbach
8c454cac49
Tests for 142365.
...
llvm-svn: 142368
2011-10-18 17:23:34 +00:00
Jim Grosbach
df6fb84ea5
Tidy up formatting.
...
llvm-svn: 142367
2011-10-18 17:22:53 +00:00
Jim Grosbach
031bb99231
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
Jim Grosbach
9266437a1f
Enable a few more NEON immediate tests.
...
llvm-svn: 142313
2011-10-17 23:50:19 +00:00
Jim Grosbach
1e994e76a7
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
Jim Grosbach
f3d495fbbd
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
Owen Anderson
96976108b1
Update test for disabling of code/data marker labels in ELF.
...
llvm-svn: 142003
2011-10-14 21:12:55 +00:00
Jim Grosbach
422576b6e8
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
Jim Grosbach
2a501996ab
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
Jim Grosbach
d2cfc2b31f
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
Jim Grosbach
6322a90e2d
Enable ARM mode VDUP(scalar) tests.
...
llvm-svn: 141447
2011-10-07 23:57:03 +00:00
Jim Grosbach
94980a23e6
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
Jim Grosbach
53b2b56db8
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
...
llvm-svn: 141321
2011-10-06 22:04:05 +00:00
Jim Grosbach
ec12700fe4
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141318
2011-10-06 21:32:50 +00:00
Jim Grosbach
17ae6aae38
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141316
2011-10-06 21:28:30 +00:00
Owen Anderson
2d1e930b65
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
Owen Anderson
e255773f3d
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
Jim Grosbach
386f7cb041
Tidy up formatting.
...
llvm-svn: 141123
2011-10-04 21:43:51 +00:00
Jim Grosbach
f3373734b4
Un-XFAIL file. Comment out individual failing instructions.
...
llvm-svn: 141117
2011-10-04 21:16:42 +00:00
Jim Grosbach
6f00406f92
Tidy up formatting.
...
llvm-svn: 141115
2011-10-04 20:52:57 +00:00
Jim Grosbach
0db58d15e6
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
...
llvm-svn: 141114
2011-10-04 20:50:05 +00:00
Jim Grosbach
3df5c47ec8
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
...
llvm-svn: 141113
2011-10-04 20:46:49 +00:00
Jim Grosbach
4770714494
Tidy up formatting.
...
llvm-svn: 141111
2011-10-04 20:42:35 +00:00
Jim Grosbach
dee6bd4517
Un-XFAIL file. Fix incorrect CHECK line.
...
llvm-svn: 141110
2011-10-04 20:42:09 +00:00
Jim Grosbach
d7449dd23f
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141108
2011-10-04 20:34:11 +00:00
Jim Grosbach
58f067b61b
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141099
2011-10-04 18:43:15 +00:00
Jim Grosbach
93ad98accb
Tidy up. Formatting.
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llvm-svn: 141096
2011-10-04 17:49:45 +00:00
Jim Grosbach
8170db143e
Tidy up. These tests are covered in the .s file tests now.
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llvm-svn: 141047
2011-10-03 23:40:13 +00:00
Jim Grosbach
f38874e79e
ARM assembly parsing and encoding for VMOV immediate.
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llvm-svn: 141046
2011-10-03 23:38:36 +00:00
Jim Grosbach
c69258c747
ARM parsing/encoding for VCMP/VCMPE.
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llvm-svn: 141038
2011-10-03 22:30:24 +00:00
Jim Grosbach
21a9f8f50f
ARM assembly parsing and encoding for VMRS/FMSTAT.
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llvm-svn: 141025
2011-10-03 21:12:43 +00:00
Jim Grosbach
0e385170ee
Update test for 141010.
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llvm-svn: 141022
2011-10-03 20:58:08 +00:00
Jim Grosbach
1651804363
Tidy up a bit. Formatting.
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llvm-svn: 141010
2011-10-03 17:59:31 +00:00
James Molloy
c4fcff419c
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
Jim Grosbach
b503a2183e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
Owen Anderson
c811b1bed2
Remove incorrect testcases.
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llvm-svn: 140572
2011-09-26 22:13:55 +00:00
Owen Anderson
fc9a0d104c
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
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llvm-svn: 140426
2011-09-23 22:25:02 +00:00
Owen Anderson
22ab29756b
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
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llvm-svn: 140284
2011-09-21 23:53:44 +00:00
Jim Grosbach
dd8f345dc3
Nuke obsolete test file.
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llvm-svn: 140127
2011-09-20 01:03:51 +00:00
Jim Grosbach
169f556004
Thumb2 assembly parsing and encoding for WFE/WFI/YIELD.
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llvm-svn: 140126
2011-09-20 00:48:56 +00:00
Jim Grosbach
e936bdc286
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
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llvm-svn: 140125
2011-09-20 00:46:54 +00:00
Jim Grosbach
79dac4bf28
Thumb2 assembly parsing and encoding for USUB8/USUB16.
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llvm-svn: 140120
2011-09-20 00:31:57 +00:00
Jim Grosbach
5ca3bddd26
Thumb2 assembly parsing and encoding for USAX.
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llvm-svn: 140119
2011-09-20 00:30:45 +00:00
Jim Grosbach
f6d79c7c40
Thumb2 assembly parsing and encoding for USAT16.
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llvm-svn: 140118
2011-09-20 00:28:25 +00:00
Jim Grosbach
4768b6b0d4
Thumb2 assembly parsing and encoding for USAT.
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llvm-svn: 140117
2011-09-20 00:27:36 +00:00
Jim Grosbach
d9a8af05ea
Tidy up.
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llvm-svn: 140114
2011-09-20 00:24:37 +00:00
Jim Grosbach
c67e9e9885
Thumb2 assembly parsing and encoding for UQSAD8/USADA8.
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llvm-svn: 140113
2011-09-20 00:23:51 +00:00
Jim Grosbach
0b329532eb
Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8.
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llvm-svn: 140112
2011-09-20 00:20:44 +00:00
Jim Grosbach
18a65f1fe6
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
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llvm-svn: 140111
2011-09-20 00:18:52 +00:00
Jim Grosbach
f5f3242925
Thumb2 assembly parsing and encoding for UQADD16/UQADD8.
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llvm-svn: 140110
2011-09-20 00:15:03 +00:00
Jim Grosbach
d4a347b1e8
Tidy up a bit.
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llvm-svn: 140096
2011-09-19 23:34:18 +00:00
Jim Grosbach
2341e082fc
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
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llvm-svn: 140095
2011-09-19 23:31:02 +00:00
Jim Grosbach
3a7a6c8acf
Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8.
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llvm-svn: 140089
2011-09-19 23:15:36 +00:00
Jim Grosbach
dd8d66f3aa
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
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llvm-svn: 140088
2011-09-19 23:13:25 +00:00
Jim Grosbach
0bec90ffe5
Thumb2 assembly parsing and encoding for UHADD16/UHADD8.
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llvm-svn: 140087
2011-09-19 23:08:24 +00:00
Jim Grosbach
ec1bd1e213
Thumb2 assembly parsing and encoding for UBFX.
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llvm-svn: 140086
2011-09-19 23:06:38 +00:00
Jim Grosbach
a5a28c45e5
Thumb2 assembly parsing and encoding for UASX.
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llvm-svn: 140085
2011-09-19 23:05:22 +00:00
Jim Grosbach
4d8d362374
Fix copy/past-o. Gotta remember that 'modify' step...
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llvm-svn: 140082
2011-09-19 22:53:00 +00:00
Jim Grosbach
2ef3c31987
Thumb2 assembly parsing and encoding for UADD16/UADD8.
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llvm-svn: 140081
2011-09-19 22:52:27 +00:00
Jim Grosbach
7941ca00ab
Thumb2 assembly parsing and encoding for TST.
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llvm-svn: 140080
2011-09-19 22:46:06 +00:00
Jim Grosbach
6da9e6b23d
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
Jim Grosbach
2185babd50
Thumb2 assembly parsing and encoding for TEQ.
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llvm-svn: 140070
2011-09-19 21:41:21 +00:00
Jim Grosbach
6e092f297b
Remove FIXME. TBB/TBH are Thumb mode only instructions.
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llvm-svn: 140048
2011-09-19 20:30:29 +00:00
Jim Grosbach
c7fa5f0c00
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
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llvm-svn: 140047
2011-09-19 20:29:33 +00:00
Jim Grosbach
c677995374
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
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llvm-svn: 140029
2011-09-19 17:56:37 +00:00
Jim Grosbach
06677b6b4c
Thumb2 assembly parsing and encoding for SVC.
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llvm-svn: 140025
2011-09-19 17:40:35 +00:00
Jim Grosbach
a5bdf3b221
Thumb2 assembly parsing and encoding for SUB(register).
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llvm-svn: 140024
2011-09-19 17:37:48 +00:00
Jim Grosbach
95242bff08
Thumb2 assembly parsing and encoding for SUB(immediate).
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llvm-svn: 139966
2011-09-16 22:58:42 +00:00
Jim Grosbach
3a58f722bf
Thumb2 assembly parsing and encoding for STRT.
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llvm-svn: 139963
2011-09-16 22:27:12 +00:00
Jim Grosbach
41ece87fae
Thumb2 assembly parsing and encoding for LDRHT/STRHT.
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llvm-svn: 139962
2011-09-16 22:26:01 +00:00
Jim Grosbach
e9f1da5dec
Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD.
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llvm-svn: 139961
2011-09-16 22:22:07 +00:00
Jim Grosbach
f8313f60b3
Thumb2 assembly parsing and encoding for STRD.
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llvm-svn: 139960
2011-09-16 22:19:38 +00:00
Jim Grosbach
d0ef17692a
Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only.
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llvm-svn: 139959
2011-09-16 22:18:42 +00:00
Jim Grosbach
c3834c5da5
Thumb2 assembly parsing and encoding for STRBT.
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llvm-svn: 139957
2011-09-16 22:15:51 +00:00
Jim Grosbach
3caa04dc32
Thumb2 assembly parsing and encoding for STRH.
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llvm-svn: 139956
2011-09-16 22:12:19 +00:00
Jim Grosbach
771b6c5fe3
Remove test of undocumented format.
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llvm-svn: 139955
2011-09-16 22:09:58 +00:00
Jim Grosbach
b181e68ab6
Thumb2 assembly parsing and encoding for STRB.
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llvm-svn: 139954
2011-09-16 22:09:19 +00:00
Jim Grosbach
f75d317df4
Shuffle a few more thumb2 tests to match the comment headings.
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llvm-svn: 139952
2011-09-16 22:01:18 +00:00
Jim Grosbach
bc84a55ed8
Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate.
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llvm-svn: 139951
2011-09-16 21:59:13 +00:00
Jim Grosbach
c9eb37a7c9
Shuffle a few tests around.
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llvm-svn: 139950
2011-09-16 21:57:10 +00:00
Jim Grosbach
916a6c71aa
Thumb2 assembly parsing and encoding for STR(immediate).
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Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
Jim Grosbach
03c39637ee
Thumb2 assembly parsing and encoding for STMDB.
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llvm-svn: 139940
2011-09-16 20:58:38 +00:00
Jim Grosbach
13af7198d5
Thumb2 assembly parsing and encoding for STMIA.
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llvm-svn: 139938
2011-09-16 20:50:13 +00:00
Jim Grosbach
0c71c46758
Thumb2 assembly parsing and encoding for SSUB16/SSUB8.
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llvm-svn: 139931
2011-09-16 18:52:36 +00:00
Jim Grosbach
47ff106753
Thumb2 assembly parsing and encoding for SSAX.
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llvm-svn: 139929
2011-09-16 18:37:10 +00:00
Jim Grosbach
eb47e416c2
Thumb2 assembly parsing and encoding for SSAT16.
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llvm-svn: 139927
2011-09-16 18:33:22 +00:00
Jim Grosbach
6f6453f64b
Thumb2 assembly parsing and encoding for SSAT.
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llvm-svn: 139926
2011-09-16 18:32:30 +00:00
Jim Grosbach
5a8b63fe51
Thumb2 assembly parsing and encoding for SRS.
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llvm-svn: 139925
2011-09-16 18:25:22 +00:00
Jim Grosbach
3cac04dd75
Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX.
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llvm-svn: 139923
2011-09-16 18:08:48 +00:00
Jim Grosbach
b8b9febaa7
Thumb2 assembly parsing and encoding for SMMULWB/SMULWT.
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llvm-svn: 139922
2011-09-16 18:07:18 +00:00
Jim Grosbach
0f1615c381
Thumb2 assembly parsing and encoding for SMMULL.
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llvm-svn: 139921
2011-09-16 18:05:48 +00:00
Jim Grosbach
4c944a22e2
Fix comment.
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llvm-svn: 139919
2011-09-16 18:03:00 +00:00
Jim Grosbach
f39a3fcb4f
Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT.
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llvm-svn: 139918
2011-09-16 18:02:36 +00:00
Jim Grosbach
0066bd4289
Thumb2 assembly parsing and encoding for SMMUAD'dib.
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llvm-svn: 139917
2011-09-16 17:58:21 +00:00
Jim Grosbach
89777cb2f9
Thumb2 assembly parsing and encoding for SMMUL/SMMULR.
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llvm-svn: 139916
2011-09-16 17:56:06 +00:00
Jim Grosbach
fa3986ddbe
Thumb2 assembly parsing and encoding for SMMLS/SMMLSR.
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llvm-svn: 139911
2011-09-16 17:16:55 +00:00
Jim Grosbach
25e57a3e7a
Thumb2 assembly parsing and encoding for SMMLA/SMMLAR.
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llvm-svn: 139910
2011-09-16 17:15:18 +00:00
Jim Grosbach
3c3a9393ab
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
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llvm-svn: 139909
2011-09-16 17:10:44 +00:00
Jim Grosbach
5d7af41c05
Thumb2 assembly parsing and encoding for SMLSD/SMLSDX.
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llvm-svn: 139908
2011-09-16 17:08:45 +00:00
Jim Grosbach
599dd49609
Thumb2 assembly parsing and encoding for SMLAWB/SMLAWT.
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llvm-svn: 139907
2011-09-16 17:03:01 +00:00
Jim Grosbach
9e471afd9c
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
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llvm-svn: 139906
2011-09-16 16:58:03 +00:00
Jim Grosbach
77ece5c9a0
Thumb2 assembly parsing and encoding for SMLALBB/SMLALBT/SMLALTB/SMLALTT.
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llvm-svn: 139905
2011-09-16 16:53:25 +00:00
Jim Grosbach
d382581509
Thumb2 assembly parsing and encoding for SMLAL.
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llvm-svn: 139902
2011-09-16 16:38:00 +00:00
Jim Grosbach
5147a59e59
Thumb2 assembly parsing and encoding for SMLAD/SMLADX.
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llvm-svn: 139884
2011-09-16 00:09:37 +00:00