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627 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
8df123273d Mark ldrexd/strexd w/ volatile memory by default 
llvm-svn: 133175
 2011-06-16 18:11:32 +00:00
Chad Rosier
66fa658a4b Revision r128665 added an optimization to make use of NEON multiplier 
accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.

llvm-svn: 133127
 2011-06-16 01:21:54 +00:00
Bob Wilson
767e3a6971 A minor simplification: no functional change. 
llvm-svn: 133047
 2011-06-15 06:04:34 +00:00
Evan Cheng
7624839811 PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 
the bits being cleared by the AND are not demanded by the BFI.

The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).

rdar://9609030

llvm-svn: 133034
 2011-06-15 01:12:31 +00:00
Tanya Lattner
5ee64fc868 Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add. 
Includes a test case.

llvm-svn: 133027
 2011-06-14 23:48:48 +00:00
Bruno Cardoso Lopes
b6afc5168f Add one more argument to the prefetch intrinsic to indicate whether it's a data 
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976
 2011-06-14 04:58:37 +00:00
Cameron Zwarich
a54eaeb7ae Provide an ARMCCState subclass of CCState so that ARM clients will always set 
CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856
 2011-06-10 20:59:24 +00:00
Cameron Zwarich
af47f4a117 A CCState was being created without setting whether it is in the Call or Prologue state, 
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811
 2011-06-09 22:30:07 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Eric Christopher
e831655dd9 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
 2011-06-03 17:24:37 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939

llvm-svn: 132510
 2011-06-02 23:16:42 +00:00
John McCall
64ff21faa7 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.

llvm-svn: 132295
 2011-05-29 19:50:32 +00:00
John McCall
ffdb2d5e70 I didn't mean to commit these residues of a personal project. 
llvm-svn: 132293
 2011-05-29 19:41:56 +00:00
John McCall
46c7b963b2 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

llvm-svn: 132291
 2011-05-29 19:39:04 +00:00
Bruno Cardoso Lopes
6d5e369a10 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248
 2011-05-28 04:07:29 +00:00
Cameron Zwarich
cd3c1b5829 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

llvm-svn: 132235
 2011-05-27 23:54:00 +00:00
Evan Cheng
0fcb465bab Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
llvm-svn: 132211
 2011-05-27 20:11:27 +00:00
Renato Golin
759db3cbe3 RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
llvm-svn: 131868
 2011-05-22 21:41:23 +00:00
Evan Cheng
9dbb570612 Revert accidental commit. 
llvm-svn: 131739
 2011-05-20 17:38:48 +00:00
Evan Cheng
a3f5204c82 Revert r131664 and fix it in instcombine instead. rdar://9467055 
llvm-svn: 131708
 2011-05-20 00:54:37 +00:00
Mon P Wang
9c138e7a7d Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
llvm-svn: 131630
 2011-05-19 04:15:07 +00:00
Tanya Lattner
6814933ea6 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.

llvm-svn: 131582
 2011-05-18 21:44:54 +00:00
Evan Cheng
4787dc8f70 Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
llvm-svn: 131555
 2011-05-18 18:59:17 +00:00
Evan Cheng
ea3c2f0e60 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
llvm-svn: 131553
 2011-05-18 18:47:27 +00:00
Tanya Lattner
06cb9cbf98 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
b89a768a61 Fix typo. 
llvm-svn: 131519
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
b922060f98 Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

llvm-svn: 131518
 2011-05-18 02:20:07 +00:00
Bill Wendling
453a924d29 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>

llvm-svn: 131174
 2011-05-11 01:11:55 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Bob Wilson
7ca16f2c1f Temporarily disable use of divmod compiler-rt functions for iOS. 
llvm-svn: 130766
 2011-05-03 17:33:22 +00:00
Dan Gohman
7beb845bab Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743
 2011-05-03 00:46:49 +00:00
Eric Christopher
ad02f6c78a 80-col. 
llvm-svn: 130558
 2011-04-29 23:12:01 +00:00
Jim Grosbach
77d45564c3 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019

llvm-svn: 130234
 2011-04-26 19:44:18 +00:00
Andrew Trick
a130d110d1 Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).

llvm-svn: 130048
 2011-04-23 03:55:32 +00:00
Evan Cheng
28877b11a2 Remove -use-divmod-libcall. Let targets opt in when they are available. 
llvm-svn: 129884
 2011-04-20 22:20:12 +00:00
Stuart Hastings
1905cf10e3 Excise unintended hunk in 129858. <rdar://problem/7662569> 
llvm-svn: 129862
 2011-04-20 18:09:26 +00:00
Stuart Hastings
a552942e02 ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
llvm-svn: 129858
 2011-04-20 16:47:52 +00:00
Eric Christopher
21ad2325df Remove some duplicate op action entries and reorganize. 
llvm-svn: 129781
 2011-04-19 18:49:19 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Evan Cheng
f33f509d45 Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902

llvm-svn: 129556
 2011-04-15 01:31:00 +00:00
Cameron Zwarich
6b4e85338c Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
llvm-svn: 129468
 2011-04-13 21:01:19 +00:00
Cameron Zwarich
c05412175e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345
 2011-04-12 02:24:17 +00:00
Evan Cheng
bc053100af Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Evan Cheng
9049eb2113 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Tanya Lattner
3deb96fad7 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Evan Cheng
859dff2c87 Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Owen Anderson
b59504a1a1 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
llvm-svn: 128965
 2011-04-05 23:55:28 +00:00
Owen Anderson
c8ceb7246f Revert r128946 while I figure out why it broke the buildbots. 
llvm-svn: 128951
 2011-04-05 23:03:06 +00:00
Owen Anderson
809f1a74d1 Give RSBS and RSCS the pseudo treatment. 
llvm-svn: 128946
 2011-04-05 22:42:54 +00:00
Owen Anderson
b73d1741c6 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
llvm-svn: 128940
 2011-04-05 21:48:57 +00:00