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Commit Graph

218839 Commits

Author SHA1 Message Date
Sander de Smalen
50816080ef Revert "[LV] Print remark when loop cannot be vectorized due to invalid costs."
This reverts commit efaf3099c8cec1954831ee28a2f75a72096f50eb.
This reverts commit dc7bdc1e7121693df112f2fdb11cc6b88580ba4b.

Reverting patches due to buildbot failures.
2021-07-15 15:21:57 +01:00
Nathan Sidwell
83135ce4f4 [docs] More CMAKE variable documentation
This breaks out some (more) common llvm-specific
variables. Controlling the subprojects and target architectures, along
with clues about restricting build parallelism when linking. 'more
common' is somewhat subjective, of course.

Differential Revision: https://reviews.llvm.org/D105822
2021-07-15 06:56:49 -07:00
David Green
47a6aacab4 [ARM] Expand types handled in VQDMULH recognition
We have a DAG combine for recognizing the sequence of nodes that make up
an MVE VQDMULH, but only currently handles specifically legal types.
This patch expands that to other power-2 vector types. For smaller than
legal types this means any_extending the type and casting it to a legal
type, using a VQDMULH where we only use some of the lanes. The result is
sign extended back to the original type, to properly set the invalid
lanes. Larger than legal types are split into chunks with extracts and
concat back together.

Differential Revision: https://reviews.llvm.org/D105814
2021-07-15 14:47:53 +01:00
Tim Northover
9bdb647741 MachO: don't emit L... private symbols in do_not_dead_strip sections.
The linker can sometimes drop the do_not_dead_strip if it can't associate the
atom with a symbol (the other place to specify no dead-stripping in MachO
files).
2021-07-15 14:40:43 +01:00
Roman Lebedev
5a590be916 [SimplifyCFG] Rerun PHI deduplication after common code sinkinkg (PR51092)
`SinkCommonCodeFromPredecessors()` doesn't itself ensure that duplicate PHI nodes aren't created.
I suppose, we could teach it to do that on-the-fly (& account for the already-existing PHI nodes,
& adjust costmodel), the diff will be bigger than this.

The alternative is to schedule a new EarlyCSE pass invocation somewhere later in the pipeline.
Clearly, we don't have any EarlyCSE runs in module optimization passline, so this pattern isn't cleaned up...
That would perhaps better, but it will again have some compile time impact.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D106010
2021-07-15 16:34:34 +03:00
Simon Pilgrim
87679ebe78 [TTI] Consistently make getMinVectorRegisterBitWidth() methods const. NFCI.
The underlying getMinVectorRegisterBitWidth() methods are const, but it was missed in a couple of TargetTransformInfo wrappers.

Noticed while working on D103925
2021-07-15 13:27:55 +01:00
Sander de Smalen
fe1fe35455 [LV] Fix determinism for failing scalable-call.ll test.
The sort function for emitting an OptRemark was not deterministic,
which caused scalable-call.ll to fail on some buildbots. This patch
fixes that.

This patch also fixes an issue where `Instruction::comesBefore()`
is called when two Instructions are in different basic blocks,
which would otherwise cause an assertion failure.
2021-07-15 13:16:59 +01:00
Stephen Tozer
a972fea3c6 Reapply "[DebugInfo] Enable variadic debug value salvaging"
Reapplied after previous build failures were fixed in 14b62f7e2.

This reverts commit 540b4a5fb31086b6d40735e96e6ec497022107e7.
2021-07-15 12:54:51 +01:00
Fraser Cormack
033e597afe [VP][NFC] Correct formatting in unit test 2021-07-15 12:38:47 +01:00
Simon Pilgrim
ac23ae72cc [NVPTX] Add selp.f32 checks to select(cond,fpbinop(),fpbinop()) tests
Will help show codegen diffs in an upcoming patch
2021-07-15 12:42:29 +01:00
Simon Pilgrim
446183aa1c [InstCombine] Strip inbounds from (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) fold
As discussed on rGd561b6fbdbe6, we can't guarantee that the new gep is inbounds
2021-07-15 12:19:10 +01:00
Simon Pilgrim
7c3ad31154 [MIPS] Refresh ashr test checks. NFCI. 2021-07-15 12:12:19 +01:00
Irina Dobrescu
16f19bf26e [AArch64][GlobalISel] Optimise lowering for some vector types for min/max
Differential Revision: https://reviews.llvm.org/D105696
2021-07-15 11:34:32 +01:00
Sebastian Neubauer
b992832f74 [AMDGPU] Use isMetaInstruction for instruction size
Meta instructions have a size of 0. Use isMetaInstruction instead of
listing them explicitly.

Differential Revision: https://reviews.llvm.org/D106043
2021-07-15 12:23:11 +02:00
Ilya Leoshkevich
3a1b644428 [TSan] Add SystemZ longjmp support
Implement the interceptor and stack pointer demangling.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
2021-07-15 12:18:48 +02:00
Ilya Leoshkevich
b0ff945d9d [TSan] Use zeroext for function parameters
SystemZ ABI requires zero-extending function parameters to 64-bit. The
compiler is free to optimize the code around this assumption, e.g.
failing to zero-extend __tsan_atomic32_load()'s morder may cause
crashes in to_mo() switch table lookup.

Fix by adding zeroext attributes to TSan's FunctionCallees, similar to
how it was done in commit 3bc439bdff8b ("[MSan] Add instrumentation for
SystemZ"). This is a no-op on arches that don't need it.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
2021-07-15 12:18:47 +02:00
Max Kazantsev
4863909bb0 [Test] We can benefit from pipelining of ymm load/stores
This patch demonstrates a scenario when we need to load/store a single
64-byte value, which is done by 2 ymm loads and stores in AVX. The current
codegen choses the following sequence:

  load ymm0
  load ymm1
  store ymm1
  store ymm0

If we instead stored ymm0 before ymm1, we could execute 2nd load and 1st store
in parallel.
2021-07-15 17:15:14 +07:00
Cullen Rhodes
c55c74c634 [AArch64][SME] Add outer product instructions
This patch adds support for the following outer product instructions:

  * BFMOPA, BFMOPS, FMOPA, FMOPS, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA,
    UMOPS, USMOPA, USMOPS.

Depends on D105570.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105571
2021-07-15 09:51:06 +00:00
Florian Mayer
f4bb75377e [NFC] [hwasan] Split argument logic into functions.
Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105971
2021-07-15 10:45:43 +01:00
Bogdan Graur
baec013412 Fixes memory sanitizer 'use-of-uninitialized-value' diagnostic.
Differential Revision: https://reviews.llvm.org/D106047
2021-07-15 11:17:04 +02:00
Timm Bäder
0108938558 [llvm][tools] Hide unrelated llvm-bcanalyzer options
They otherwise show up when we link against the dynamic libLLVM.so.

Differential Revision: https://reviews.llvm.org/D105893
2021-07-15 10:43:15 +02:00
LLVM GN Syncbot
091d61e196 [gn build] Port b0d38ad0bc25 2021-07-15 07:50:35 +00:00
Djordje Todorovic
140c795b75 [2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs
This patch adds the forward scan for finding redundant DBG_VALUEs.

This analysis aims to remove redundant DBG_VALUEs by going forward
in the basic block by considering the first DBG_VALUE as a valid
until its first (location) operand is not clobbered/modified.
For example:

(1) DBG_VALUE $edi, !"var1", ...
(2) <block of code that does affect $edi>
(3) DBG_VALUE $edi, !"var1", ...
 ...
in this case, we can remove (3).

Differential Revision: https://reviews.llvm.org/D105280
2021-07-15 00:08:31 -07:00
Tony Tye
57b2fbab2e [AMDGPU] Reserve AMDGPU ELF e_flags machine 0x44
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D106034
2021-07-15 06:46:27 +00:00
Chuanqi Xu
ca13ea7edf [Coroutines] Run coroutine passes by default
This patch make coroutine passes run by default in LLVM pipeline. Now
the clang and opt could handle IR inputs containing coroutine intrinsics
without special options.
It should be fine. On the one hand, the coroutine passes seems to be stable
since there are already many projects using coroutine feature.
On the other hand, the coroutine passes should do nothing for IR who doesn't
contain coroutine intrinsic.

Test Plan: check-llvm

Reviewed by: lxfind, aeubanks

Differential Revision: https://reviews.llvm.org/D105877
2021-07-15 14:33:40 +08:00
Kuter Dinel
b86b597e6c [Attributor] AACallEdges, Add a way to ask nonasm unknown callees
This patch adds a feature to AACallEdges AbstractAttribute that allows
users to ask if there is a unknown callee that isn't a inline assembly.
This feature is needed by some of it's users.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105992
2021-07-15 06:10:42 +03:00
Chen Zheng
90f3c2e043 [PowerPC][NFC] add testcase for update-form preparation with non-const increment 2021-07-15 02:46:24 +00:00
LLVM GN Syncbot
9865f77f6d [gn build] Port b9c3941cd61d 2021-07-15 01:12:36 +00:00
Kai Luo
bb52bc77a5 [PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand
This patch uses AtomicExpandPass to implement quadword lock free atomic operations. It adopts the method introduced in https://reviews.llvm.org/D47882, which expand atomic operations post RA to avoid spilling that might prevent LL/SC progress.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103614
2021-07-15 01:12:09 +00:00
Kuter Dinel
bfdc40f15b [AMDGPU] Use update_test_checks.py script for annotate kernel features tests.
This patch makes the annotate kernel features tests use the update_tests_checks.py
script. Which makes it easy to update the tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D105864
2021-07-15 03:13:37 +03:00
Thomas Lively
3c50e4a7a7 [WebAssembly] Codegen for v128.storeX_lane instructions
Replace the experimental clang builtins and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50435.

Differential Revision: https://reviews.llvm.org/D106019
2021-07-14 16:15:25 -07:00
Jon Roelofs
daf8a095a1 [GlobalOpt] Fix a miscompile when evaluating struct initializers.
The bug was that evaluateBitcastFromPtr attempts a narrowing to a struct's 0th
element of a store that covers other elements. While this is okay on the load
side, applying it to stores causes us to miss the writes to the additionally
covered elements.

rdar://79503568

Differential revision: https://reviews.llvm.org/D105838
2021-07-14 15:37:01 -07:00
Steven Wu
d31e29ae39 [Support] Turn on SupportTest for Apple Silicon
Follow up for D106012, turn on unittest for Host on Apple Silicon.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D106020
2021-07-14 15:24:56 -07:00
Arthur Eubanks
f5788bb9c7 [docs][OpaquePtr] Remove finished task 2021-07-14 14:36:41 -07:00
Wolfgang Pieb
bf7a422513 [ARM] Fix RELA relocations for 32bit ARM.
RELA relocations for 32 bit ARM ignored the addend. Some tools generate
them instead of REL type relocations. This fixes PR50473.

    Reviewed By: MaskRay, peter.smith

    Differential Revision: https://reviews.llvm.org/D105214
2021-07-14 14:27:15 -07:00
Derek Schuff
f708d3928c [llvm-strip][WebAssembly] Support strip flags
Summary:
Add support for the basic section stripping (and keeping) flags for wasm:
strip with no flags, --strip-all, --strip-debug,
--only-section, --keep-section, and --only-keep-debug.

Factor section removal into a function and use a predicate chain like
the ELF implementation.

Reviewers: jhenderson, sbc100

Differential Revision: https://reviews.llvm.org/D73820
2021-07-14 14:17:02 -07:00
Arthur Eubanks
a8da5bdd63 Precommit test for D106017 2021-07-14 14:14:49 -07:00
Arthur Eubanks
9d99a13a85 [SimpleLoopUnswitch] Don't non-trivially unswitch loops with catchswitch exits
SplitBlock() can't handle catchswitch.

Fixes PR50973.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D105672
2021-07-14 14:07:28 -07:00
Jon Roelofs
ffc7470172 [AArch64] Fix selection of G_UNMERGE <2 x s16>
Differential revision: https://reviews.llvm.org/D106007
2021-07-14 13:40:56 -07:00
Philip Reames
99a7d1e6cf [tests] Stablize tests for possible change in deref semantics
This is conceptually part of e75a2dfe.  This file contains both tests whose results don't change (with the right attributes added), and tests which fundementally regress with the current proposal.  Doing the update took some care, thus the seperate change.

Here's the e75a2dfe context repeated:

There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
2021-07-14 13:37:50 -07:00
Steven Wu
9c64643022 [Support] Get correct number of physical cores on Apple Silicon
Fix a bug that `computeHostNumPhysicalCores` is fallback to default
unknown when building for Apple Silicon macs.

rdar://80533675

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D106012
2021-07-14 13:29:54 -07:00
Philip Reames
652d77cf2f Global variables with strong definitions cannot be freed
With the current deref semantics, this is redundant - since we assume that anything which is dereferenceable (ever) can't be freed - but it becomes neccessary for the deref-at-point semantics.

Testing wise, this is covered by test/CodeGen/X86/hoist-invariant-load.ll when -use-dereferenceable-at-point-semantics is active.  I didn't bother duplicating the command line since a) it's an in-development mode, and b) the change is pretty obvious.
2021-07-14 13:26:18 -07:00
Philip Reames
b12ecd2ebd [tests] Stablize tests for possible change in deref semantics
There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
2021-07-14 13:05:43 -07:00
Stanislav Mekhanoshin
1dae83cabb [AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization
Any def of EXEC prevents rematerialization of any VOP instruction
because of the physreg use. Create a callback to check if the
physreg use can be ingored to allow rematerialization.

Differential Revision: https://reviews.llvm.org/D105836
2021-07-14 13:03:58 -07:00
Alexey Bataev
79d83636b9 [SLP][NFC]Fix variables names, NFC. 2021-07-14 12:43:45 -07:00
Fangrui Song
f00933b0e4 [docs] Fix :option:--file-header reference in llvm-readelf.rst after D105532 2021-07-14 12:39:22 -07:00
Simon Pilgrim
dd97f9edd3 [SLP] Fix case of variable name. NFCI. 2021-07-14 20:20:04 +01:00
Roman Lebedev
60d35e606c [NFC] Drop redundant check prefixes in newly added test file 2021-07-14 22:14:36 +03:00
Nikita Popov
0b8ca13018 [Attributes] Use single method to fetch type from AttributeSet (NFC)
While it is nice to have separate methods in the public AttributeSet
API, we can fetch the type from the internal AttributeSetNode
using a generic API for all type attribute kinds.
2021-07-14 21:10:56 +02:00
Roman Lebedev
c64b97d8cf [NFC][PhaseOrdering] Add test for the lack of CSE after SimplifyCFG (PR51092) 2021-07-14 22:07:38 +03:00