Elena Demikhovsky
194da7364d
Added FMA3 Intel instructions.
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I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
llvm-svn: 157737
2012-05-31 09:20:20 +00:00
Benjamin Kramer
0c823ae0ed
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
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This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
Craig Topper
55b5aa4042
Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended.
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llvm-svn: 157122
2012-05-19 19:14:18 +00:00
Jim Grosbach
2e62e2f664
Allow MCCodeEmitter access to the target MCRegisterInfo.
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Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
llvm-svn: 156828
2012-05-15 17:35:52 +00:00
Joerg Sonnenberger
4df2738e5f
Put Is64BitMemOperand into !defined(NDEBUG) for now.
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llvm-svn: 153185
2012-03-21 14:09:26 +00:00
Joerg Sonnenberger
82af1c8704
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
llvm-svn: 153166
2012-03-21 05:48:07 +00:00
Craig Topper
cfbfa3dcd1
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Craig Topper
ecf21d8132
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Anton Korobeynikov
5996573d4b
Add support for implicit TLS model used with MS VC runtime.
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Patch by Kai Nacke!
llvm-svn: 150307
2012-02-11 17:26:53 +00:00
Craig Topper
fe4a950689
Convert assert(0) to llvm_unreachable in X86 Target directory.
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llvm-svn: 149809
2012-02-05 05:38:58 +00:00
Jim Grosbach
e6ac20aadf
Keep source location information for X86 MCFixup's.
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llvm-svn: 149106
2012-01-27 00:51:27 +00:00
Craig Topper
44a5136fac
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
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llvm-svn: 147366
2011-12-30 04:48:54 +00:00
Jan Sjödin
b4602e048f
XOP encoding bits and logic.
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llvm-svn: 146397
2011-12-12 19:12:26 +00:00
Rafael Espindola
9b9d35cc05
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
Jan Sjödin
fb32802944
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
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llvm-svn: 146151
2011-12-08 14:43:19 +00:00
Bruno Cardoso Lopes
626d04cc6f
This patch contains support for encoding FMA4 instructions and
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tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
Craig Topper
0e63b4485c
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Craig Topper
6c900d9810
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper
4c6357d4af
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper
62e63d9bb9
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Bruno Cardoso Lopes
b3eab8c22d
Tidy up a bit more, fix tab and remove trailing whitespaces
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llvm-svn: 140186
2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
dab989502d
Tidy up code!
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llvm-svn: 140183
2011-09-20 21:39:06 +00:00
Bruno Cardoso Lopes
9979e44f1b
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
Bruno Cardoso Lopes
306110c29a
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
Evan Cheng
04762a3cf5
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
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This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jeffrey Yasskin
8a0f9f17a3
Explicitly cast narrowing conversions inside {}s that will become errors in
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C++0x.
llvm-svn: 136211
2011-07-27 06:22:51 +00:00
Evan Cheng
bbacc163bb
More refactoring.
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llvm-svn: 135939
2011-07-25 19:33:48 +00:00