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Commit Graph

743 Commits

Author SHA1 Message Date
Jim Grosbach
f45795436a Make assembly parser method names more consistent.
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach
402ca4879f Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.

llvm-svn: 135946
2011-07-25 20:06:30 +00:00
Jim Grosbach
2ca37e058f Tidy up a bit.
llvm-svn: 135945
2011-07-25 20:00:32 +00:00
Jim Grosbach
dd6b9fa0da ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00
Jim Grosbach
4f1031662f ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Jim Grosbach
ebd66f344c ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach
c80a7c4e75 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
2011-07-22 18:06:01 +00:00
Jim Grosbach
8168e689c0 Tidy up.
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach
98e7733a08 Tidy up.
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
Jim Grosbach
97f089a499 Tidy up.
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
Owen Anderson
e34471d064 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Jim Grosbach
e56f945492 ARM Asm parser range checking for [0,31] immediates.
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
Jim Grosbach
8d031eeb23 ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach
e96857fd4f ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach
a860ba338f ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Owen Anderson
2e26de13d2 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
Jim Grosbach
5a0277bab7 ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
Jim Grosbach
572868e146 ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Jim Grosbach
fbaaa3ae98 Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
2011-07-20 20:49:03 +00:00
Jim Grosbach
94a88152c9 ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Jim Grosbach
e70c8eb49a Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Jim Grosbach
720b8c6578 ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Jim Grosbach
66af8b4a40 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
2011-07-19 20:35:35 +00:00
Jim Grosbach
294b83e3e2 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
2011-07-19 19:13:28 +00:00
Jim Grosbach
31cda4ed6d ARM range checking for so_imm operands in assembly parsing.
llvm-svn: 135489
2011-07-19 16:50:30 +00:00
Benjamin Kramer
d88f66e018 Port operand types for ARM and X86 over from EDIS to the .td files.
llvm-svn: 135198
2011-07-14 21:47:22 +00:00
Jim Grosbach
2ab898973a ARM MCRR/MCRR2 immediate operand range checking.
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831 ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Jim Grosbach
e18641e454 Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179
2011-07-14 19:47:47 +00:00
Jim Grosbach
aebb9cdf68 Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Jim Grosbach
4b63d59acb ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach
2ee8287c62 DMB instalias needs the same predicate as the instruction.
llvm-svn: 135112
2011-07-14 00:10:26 +00:00
Jim Grosbach
5a96cebd81 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach
3eb4f0de5e Update comments. These are for assembler, too.
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
Owen Anderson
c68f12ff30 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach
93cf7d8372 Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach
4ca79b8d2c Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach
0caa098513 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach
ab030d8a81 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach
9e021b5281 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
7dbb39dffa Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
93f2ebb5e7 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jim Grosbach
c16ddf517d Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.

llvm-svn: 134727
2011-07-08 20:13:35 +00:00
Jim Grosbach
435ca7304c Use ARMPseudoExpand for ARM tail calls.
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
Jim Grosbach
8fa5e7605f Shuffle productions around a bit.
No functional change.

llvm-svn: 134714
2011-07-08 18:26:27 +00:00
Jim Grosbach
0256b8b41f Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00