1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Commit Graph

181871 Commits

Author SHA1 Message Date
Konstantin Zhuravlyov
90b0285b53 AMDGPU: Remove reserved value accidentally left in for gfx908
llvm-svn: 366101
2019-07-15 18:22:06 +00:00
Matt Arsenault
9c09b67de6 AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf
llvm-svn: 366099
2019-07-15 18:18:46 +00:00
Sanjay Patel
04af375135 [x86] try to keep FP casted+truncated+extracted vector element out of GPRs
inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0)

We have pseudo-vectorization of scalar int to FP casts, so this tries to
make that more likely by replacing a truncate with a bitcast. I didn't see
any test diffs starting from 'uitofp', so I left that as a TODO. We can't
only match the shorter trunc+extract pattern because there's an opposing
transform somewhere, so we infinite loop. Waiting to try this during
lowering is another possibility.

A motivating case is shown in PR39975 and included in the test diffs here:
https://bugs.llvm.org/show_bug.cgi?id=39975

Differential Revision: https://reviews.llvm.org/D64710

llvm-svn: 366098
2019-07-15 18:17:23 +00:00
Stella Stamenova
7c8e70034d [llvm-lib] Add a dependency to intrinsics_gen to the LLVMLibDriver build
Summary:
Occasionally the build of LLVMLibDriver will fail because Attributes.inc has not been generated yet. Add an explicit dependency, so that we can guarantee that the file has been generated before LLVMLibDriver is build.

##[error]llvm\include\llvm\IR\Attributes.h(73,0): Error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory
llvm\include\llvm/IR/Attributes.h(73): fatal error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory [LLVMLibDriver.vcxproj]

Reviewers: asmith

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64357

llvm-svn: 366097
2019-07-15 18:15:12 +00:00
Craig Topper
c34f81ed6b [X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is out of range.
I think we only turn out of range shiftss to undef when
all elements are out of range or the shift amount is a splat out
of range. I'm not sure which, I didn't check.

During lowering we can split a shift where some elements
are out of range into multiple shifts. This can create a
new shift with a splat shift amount that is out of range.

This patch returns undef for this case.

Fixes PR42615.

Differential Revision: https://reviews.llvm.org/D64699

llvm-svn: 366096
2019-07-15 17:56:57 +00:00
Matt Arsenault
8f74f32e3e AMDGPU: Add 24-bit mul intrinsics
Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

llvm-svn: 366094
2019-07-15 17:50:31 +00:00
Matt Arsenault
d421a5eebb Add some release notes for 9.0 release
llvm-svn: 366093
2019-07-15 17:50:28 +00:00
Stanislav Mekhanoshin
310633c3a3 [AMDGPU] Copy missing predicate from pseudo to real
NFC at the momemnt, needed for future commit.

Differential Revision: https://reviews.llvm.org/D64761

llvm-svn: 366092
2019-07-15 17:49:25 +00:00
Johannes Doerfert
15056cdda8 [FunctionAttrs] Remove readonly and writeonly assertion
There are scenarios where mutually recursive functions may cause the SCC
to contain both read only and write only functions. This removes an
assertion when adding read attributes which caused a crash with a the
provided test case, and instead just doesn't add the attributes.

Patch by Luke Lau <luke.lau@intel.com>

Differential Revision: https://reviews.llvm.org/D60761

llvm-svn: 366090
2019-07-15 17:31:26 +00:00
David Green
10dbfeb57f [ARM] Minor formatting in ARMInstrMVE.td. NFC
llvm-svn: 366089
2019-07-15 17:29:06 +00:00
Matt Arsenault
455c15c8d9 AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR
llvm-svn: 366087
2019-07-15 17:26:43 +00:00
Matt Arsenault
e16497490c AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS
llvm-svn: 366086
2019-07-15 17:20:40 +00:00
Sanjay Patel
b1d300b9af [x86] add tests for reductions that might be better with more horizontal ops; NFC
llvm-svn: 366082
2019-07-15 16:59:38 +00:00
Ilya Biryukov
a53e777a65 Revert "r366069: [PatternMatch] Implement matching code for LibFunc"
Reason: the change introduced a layering violation by adding a
dependency on IR to Analysis.

llvm-svn: 366081
2019-07-15 16:43:36 +00:00
James Henderson
9301c3e5a5 [docs][llvm-nm] Fix inconsistent grammar
llvm-svn: 366080
2019-07-15 16:40:34 +00:00
Simon Pilgrim
67d222fd05 [X86][SSE] Regenerated packss.ll test file.
Not sure what went wrong in rL366077....

llvm-svn: 366079
2019-07-15 16:23:42 +00:00
Simon Pilgrim
592fba5b4d [X86][SSE] Add PACKSS with zero shuffle masks.
This is an example of expansion due to D61129 - it should combine back to a PACKSS with a zero operand.

llvm-svn: 366077
2019-07-15 15:43:04 +00:00
Lang Hames
753edd65d3 [ORC] Start adding ORCv1 to ORCv2 transition tips to the ORCv2 doc.
llvm-svn: 366075
2019-07-15 15:36:37 +00:00
Stanislav Mekhanoshin
6d5b6edfdc [AMDGPU] fixed scheduler crash in gfx908
For some reason scheduler can send down an SUnit without an
instruction.

Differential Revision: https://reviews.llvm.org/D64709

llvm-svn: 366074
2019-07-15 15:34:05 +00:00
Nico Weber
dd84d5a9be gn build: Add a note on how to locally tell git to ignore build dir
llvm-svn: 366072
2019-07-15 15:14:09 +00:00
Dmitry Preobrazhensky
25b56899fa [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL message
Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D64729

llvm-svn: 366071
2019-07-15 15:12:16 +00:00
Dmitry Venikov
9729b8be9a [PatternMatch] Implement matching code for LibFunc
Summary: Provides m_LibFunc pattern that can be used to match LibFuncs.

Reviewers: spatel, hfinkel, efriedma, lebedev.ri

Reviewed By: lebedev.ri

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D42047

llvm-svn: 366069
2019-07-15 14:47:45 +00:00
Dmitry Preobrazhensky
600be1c67b [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions
See bug 42599: https://bugs.llvm.org/show_bug.cgi?id=42599

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D64716

llvm-svn: 366067
2019-07-15 14:37:57 +00:00
Simon Pilgrim
3157c926f7 [X86] isTargetShuffleEquivalent - assert the expected mask is correctly formed. NFCI.
While we don't make any assumptions about the actual mask, assert that the expected mask only contains valid mask element values.

llvm-svn: 366066
2019-07-15 14:29:14 +00:00
David Zarzycki
2eb6d2aca8 [Testing] Add missing "REQUIRES: asserts"
This broke after r366048 / https://reviews.llvm.org/D63923

llvm-svn: 366065
2019-07-15 14:12:35 +00:00
Simon Atanasyan
df3e1ef2f9 [mips] Remove "else-after-return". NFC
llvm-svn: 366064
2019-07-15 13:12:36 +00:00
Nico Weber
eb283456bc PDB HashTable: Make iterator key type const
Having the hash table key change during iteration is bad, so make it
impossible. Nothing relied on the key type not being const.

(This is also necessary to be able to call the const version of
iterator_facade_base::operator->(). Nothing calls this, and nothing
will, but I tried using it locally during development and it took me a
while to understand what was going wrong.)

Also rename the iterator typedef to const_iterator.

No behavior change.

Differential Revision: https://reviews.llvm.org/D64641

llvm-svn: 366060
2019-07-15 12:10:02 +00:00
George Rimar
13fafb5bb5 Recommit r366052 "[obj2yaml] - Rework tool's error reporting logic for ELF target."
No changes, LLD code was updated in r366057.

Original commit message:

ELF.h contains two getSymbol methods
which seems to be used only from obj2yaml.

One of these methods calls another, which in turn
contains untested error message which doesn't
provide enough information.

Problem is that after improving only just that message,
obj2yaml will not show it,
("Error reading file: yaml: Invalid data was
encountered while parsing the file" message will be shown instead),
because internal errors handling of tool is based on ErrorOr<> class which
stores a error code and as a result can only show a predefined error string, what
actually isn't very useful.

In this patch, I rework obj2yaml's error reporting system
for ELF targets to use Error  Expected<> classes.
Also, I improve the error message produced
by getSymbol for demonstration of the new functionality.

Differential revision: https://reviews.llvm.org/D64631

llvm-svn: 366058
2019-07-15 11:53:39 +00:00
David Green
0c2c6f58ea [ARM] MVE Vector Shifts
This adds basic lowering for MVE shifts. There are many shifts in MVE, but the
instructions handled here are:
 VSHL (imm)
 VSHRu (imm)
 VSHRs (imm)
 VSHL (vector)
 VSHL (register)

MVE, like NEON before it, doesn't have shift right by a vector (or register).
We instead have to negate the amount and shift in the opposite direction. This
means we have to convert any SHR's into a form of SHL (that is still signed or
unsigned) with a negated condition and selecting from there. MVE still does
have shifting by an immediate for SHL, ASR and LSR.

This adds lowering for these and for register forms, which work well for shift
lefts but may require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to potentially
work optimally for right shifts.

Differential Revision: https://reviews.llvm.org/D64212

llvm-svn: 366056
2019-07-15 11:35:39 +00:00
David Green
7944fb1dee [ARM] Move Shifts after Bits. NFC
This just moves the shift instruction definitions further down the
ARMInstrMVE.td file, to make positioning patterns slightly more natural.

llvm-svn: 366054
2019-07-15 11:22:05 +00:00
George Rimar
d8896bc316 Revert r366052 "[obj2yaml] - Rework tool's error reporting logic for ELF target."
Seems it broke LLD:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/48434

llvm-svn: 366053
2019-07-15 11:00:42 +00:00
George Rimar
f08944a915 [obj2yaml] - Rework tool's error reporting logic for ELF target.
ELF.h contains two getSymbol methods
which seems to be used only from obj2yaml.

One of these methods calls another, which in turn
contains untested error message which doesn't
provide enough information.

Problem is that after improving only just that message,
obj2yaml will not show it,
("Error reading file: yaml: Invalid data was
encountered while parsing the file" message will be shown instead),
because internal errors handling of tool is based on ErrorOr<> class which
stores a error code and as a result can only show a predefined error string, what
actually isn't very useful.

In this patch, I rework obj2yaml's error reporting system
for ELF targets to use Error  Expected<> classes.
Also, I improve the error message produced
by getSymbol for demonstration of the new functionality.

Differential revision: https://reviews.llvm.org/D64631

llvm-svn: 366052
2019-07-15 10:50:03 +00:00
David Green
8241a13714 [ARM] Adjust how NEON shifts are lowered
This adjusts the way that we lower NEON shifts to use a DAG target node, not
via a neon intrinsic. This is useful for handling MVE shifts operations in the
same the way. It also renames some of the immediate shift nodes for
consistency, and moves some of the processing of immediate shifts into
LowerShift allowing it to capture more cases.

Differential Revision: https://reviews.llvm.org/D64426

llvm-svn: 366051
2019-07-15 10:44:50 +00:00
Serguei Katkov
9ce058433d [Loop Peeling] Fix the bug with IDom setting for exit loops
It is possible that loop exit has two predecessors in a loop body.
In this case after the peeling the iDom of the exit should be a clone of
iDom of original exit but no a clone of a block coming to this exit.

Reviewers: reames, fhahn
Reviewed By: reames
Subscribers: hiraditya, zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64618

llvm-svn: 366050
2019-07-15 09:13:11 +00:00
Florian Hahn
953b5772e9 [LoopVectorize] Pass unfiltered list of arguments to getIntrinsicInstCost.
We do not compute the scalarization overhead in getVectorIntrinsicCost
and TTI::getIntrinsicInstrCost requires the full arguments list.

llvm-svn: 366049
2019-07-15 08:48:47 +00:00
Serguei Katkov
ccb2c77400 [Loop Peeling] Enable peeling for loops with multiple exits
This CL enables peeling of the loop with multiple exits where
one exit should be from latch and others are basic blocks with
call to deopt.

The peeling is enabled under the flag which is false by default.

Reviewers: reames, mkuper, iajbar, fhahn
Reviewed By: reames
Subscribers: xbolva00, hiraditya, zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D63923

llvm-svn: 366048
2019-07-15 08:26:45 +00:00
Richard Sandiford
4b201130c4 DeveloperPolicy: fix a typo
llvm-svn: 366046
2019-07-15 08:09:21 +00:00
Hideto Ueno
060abd8195 [Attributor] Deduce "nonnull" attribute
Summary:
Porting nonnull attribute to attributor.

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: xbolva00, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63604

llvm-svn: 366043
2019-07-15 06:49:04 +00:00
Serguei Katkov
cb15cb48f4 [LoopUtils] Extend the scope of getLoopEstimatedTripCount
With this patch the getLoopEstimatedTripCount function will
accept also the loops where there are more than one exit but
all exits except latch block should ends up with a call to deopt.

This side exits should not impact the estimated trip count.

Reviewers: reames, mkuper, danielcdh
Reviewed By: reames
Subscribers: fhahn, lebedev.ri, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64553

llvm-svn: 366042
2019-07-15 06:42:39 +00:00
Bill Wendling
e179425280 Remove set but unused variable.
llvm-svn: 366041
2019-07-15 06:35:28 +00:00
Serguei Katkov
b0fdbb02d2 [LoopInfo] Introduce getUniqueNonLatchExitBlocks utility function
Extract the code from LoopUnrollRuntime into utility function to
re-use it in D63923.

Reviewers: reames, mkuper
Reviewed By: reames
Subscribers: fhahn, hiraditya, zzheng, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D64548

llvm-svn: 366040
2019-07-15 05:51:10 +00:00
Fangrui Song
0bdc388713 [PowerPC] Support fp128 libcalls
On PowerPC, IEEE 754 quadruple-precision libcall names use "kf" instead of "tf".

In libgcc, libgcc/config/rs6000/float128-sed converts TF names to KF
names. This patch implements its 24 substitution rules.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D64282

llvm-svn: 366039
2019-07-15 05:02:32 +00:00
Yonghong Song
7ce6119bf4 [BPF] add unit tests for preserve_{array,union,struct}_access_index intrinsics
This is a followup patch for https://reviews.llvm.org/D61810/new/,
which adds new intrinsics preserve_{array,union,struct}_access_index.

Currently, only BPF backend utilizes preserve_{array,union,struct}_access_index
intrinsics, so all tests are compiled with BPF target.

https://reviews.llvm.org/D61524 already added some tests for these
intrinsics, but some of them pretty complex.
This patch added a few unit test cases focusing on individual intrinsic
functions.

Also made a few clarification on language reference for these intrinsics.

Differential Revision: https://reviews.llvm.org/D64606

llvm-svn: 366038
2019-07-15 04:51:34 +00:00
Kang Zhang
9732944946 [NFC][PowerPC] Add the test block-placement.mir
llvm-svn: 366037
2019-07-15 03:55:10 +00:00
Johannes Doerfert
3200affaf6 [ValueTracking] Look through constant Int2Ptr/Ptr2Int expressions
Summary:
This is analogous to the int2ptr/ptr2int instruction handling introduced
in D54956.

Reviewers: fhahn, efriedma, spatel, nlopes, sanjoy, lebedev.ri

Subscribers: hiraditya, bollu, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64708

llvm-svn: 366036
2019-07-15 03:24:35 +00:00
Craig Topper
d08e56b62d [X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
Summary:
SSE1 only supports v4f32. But does have instructions like movlps/movhps that load/store 64-bits of memory.

This patch breaks the connection between the node VT of the vzext_load/vextract_store patterns and the memory VT. Enabling a v4f32 node with a 64-bit memory VT. I've used i64 as the memory VT here. I've written the PatFrag predicate to just check the store size not the specific VT. I think the VT will only matter for CSE purposes. We could use v2f32, but if we want to start using these operations in more places a simple integer type might make the most sense.

I'd like to maybe use this same thing for SSE2 and later as well, but that will need more work to be supported by EltsFromConsecutiveLoads to avoid regressing lit tests. I'd maybe also like to combine bitcasts with these load/stores nodes now that the types are disconnected. And I'd also like to consider canonicalizing (scalar_to_vector + load) to vzext_load.

If you want I can split the mechanical tablegen stuff where I added the 32/64 off from the sse1 change.

Reviewers: spatel, RKSimon

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64528

llvm-svn: 366034
2019-07-15 02:02:31 +00:00
Alexandros Lamprineas
f5ffd2a90c [TargetParser][ARM] Account dependencies when processing target features
Teaches ARM::appendArchExtFeatures to account dependencies when processing
target features: i.e. when you say -march=armv8.1-m.main+mve.fp+nofp it
means mve.fp should get discarded too. (Split from D63936)

Differential Revision: https://reviews.llvm.org/D64048

llvm-svn: 366031
2019-07-14 20:31:15 +00:00
Florian Hahn
9d60e178aa [LV] Exclude loop-invariant inputs from scalar cost computation.
Loop invariant operands do not need to be scalarized, as we are using
the values outside the loop. We should ignore them when computing the
scalarization overhead.

Fixes PR41294

Reviewers: hsaito, rengolin, dcaballe, Ayal

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D59995

llvm-svn: 366030
2019-07-14 20:12:36 +00:00
Alexandros Lamprineas
5ef786848a [clang][Driver][ARM] Favor -mfpu over default CPU features
When processing the command line options march, mcpu and mfpu, we store
the implied target features on a vector. The change D62998 introduced a
temporary vector, where the processed features get accumulated. When
calling DecodeARMFeaturesFromCPU, which sets the default features for
the specified CPU, we certainly don't want to override the features
that have been explicitly specified on the command line. Therefore, the
default features should appear first in the final vector. This problem
became evident once I added the missing (unhandled) target features in
ARM::getExtensionFeatures.

Differential Revision: https://reviews.llvm.org/D63936

llvm-svn: 366027
2019-07-14 18:32:42 +00:00
Johannes Doerfert
79a64738c8 [GitSVN][NFC] Mark dry-run commits as such in the log output
Summary: This helps to avoid worries about the "dry run flag" while testing.

Reviewers: jyknight, rnk, mehdi_amini

Subscribers: bollu, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64697

llvm-svn: 366023
2019-07-14 18:24:19 +00:00