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Commit Graph

7278 Commits

Author SHA1 Message Date
Dale Johannesen
0ea7df37c4 Fix spelling of mtvscr and mfvscr.
llvm-svn: 40908
2007-08-07 23:08:00 +00:00
Dale Johannesen
6b8e91e7e3 Long double patch 8 of N: make it partially work in
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
2007-08-07 20:29:26 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Dale Johannesen
2c35d56edd Long double patch 7 of N, unless I lost count:).
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
2007-08-07 01:17:37 +00:00
Dale Johannesen
92be0d49fb Replace 4-line function with 10-line version per review comment.
llvm-svn: 40881
2007-08-06 22:10:35 +00:00
Dale Johannesen
4df87d9305 Move lengthy conditional down 1 level per review comment.
llvm-svn: 40878
2007-08-06 21:48:35 +00:00
Dale Johannesen
3ea9879011 Get X86 long double calling convention to work
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877
2007-08-06 21:31:06 +00:00
Dale Johannesen
e3f1d06ca0 Make 80-bit store maintain simulated FP stack correctly.
llvm-svn: 40868
2007-08-06 19:50:32 +00:00
Reid Spencer
3e54e72ef1 Fix minor doxygen nits.
llvm-svn: 40854
2007-08-05 20:06:04 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation.
Lots of problems yet but some simple things work.

llvm-svn: 40847
2007-08-05 18:49:15 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
2007-08-04 01:51:18 +00:00
Dale Johannesen
c8462173c5 Make x86 long double alignment 32 for everything but
Darwin (which makes size within a struct==96)

llvm-svn: 40796
2007-08-03 22:46:15 +00:00
Dale Johannesen
4b91728849 long double patch 2 of N. Handle it in TargetData.
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792
2007-08-03 20:20:50 +00:00
Chris Lattner
a9026e5f12 add an observation
llvm-svn: 40772
2007-08-03 00:17:42 +00:00
Dan Gohman
352de5aeb9 More explicit keywords.
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
Dan Gohman
1afde4166e Fix the alignment requirements of several unpck and shuf instructions.
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756
2007-08-02 21:17:01 +00:00
Dan Gohman
7d1e35e6d1 Fix pastos in vector arithmetic intrinsics.
llvm-svn: 40754
2007-08-02 21:06:40 +00:00
Dan Gohman
a599a813d5 Mark the SSE and MMX load instructions that
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736
2007-08-02 14:27:55 +00:00
Evan Cheng
3163814591 Switch some multiplication instructions over to the new scheme for testing.
llvm-svn: 40723
2007-08-02 05:48:35 +00:00
Evan Cheng
019ecf3b91 Can't handle offset and scale if rip-relative addressing is to be used.
llvm-svn: 40703
2007-08-01 23:46:47 +00:00
Evan Cheng
69bbf3ed2a Mac OS X X86-64 low 4G address not available.
llvm-svn: 40702
2007-08-01 23:46:10 +00:00
Evan Cheng
0fa6cdbff5 Mac OS X X86-64 low 4G address not available.
llvm-svn: 40701
2007-08-01 23:45:51 +00:00
Evan Cheng
b050c17b31 Some out operands were incorrectly specified as input operands.
llvm-svn: 40697
2007-08-01 23:07:38 +00:00
Evan Cheng
defb3b8389 Missing Requires.
llvm-svn: 40691
2007-08-01 21:42:24 +00:00
Evan Cheng
fb587a3851 Be more precise.
llvm-svn: 40689
2007-08-01 20:22:37 +00:00
Dan Gohman
8e7234519e Change a .size directive to use a tab instead of a space, for consistency.
llvm-svn: 40672
2007-08-01 14:42:30 +00:00
Evan Cheng
ab0a826b88 Indexed loads each has 2 outputs.
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
Dan Gohman
e3464e6bec Change the x86 assembly output to use tab characters to separate the
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Evan Cheng
e90ad40aa1 This isn't safe when there are uses of load's chain result.
llvm-svn: 40617
2007-07-31 06:21:44 +00:00
Dan Gohman
32ff2ca8a0 Use tabs more consistently in assembler pseudo-ops.
llvm-svn: 40594
2007-07-30 15:08:02 +00:00
Dan Gohman
23f9a3ad3b Fix the comment for getClosestTargetForJIT to reflect the fact that
it does not have a Module parameter.

llvm-svn: 40590
2007-07-30 14:58:59 +00:00
Dan Gohman
75473b49ea More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Evan Cheng
ff50061170 Vector fneg must be expanded into fsub -0.0, X.
llvm-svn: 40586
2007-07-30 07:51:22 +00:00
Christopher Lamb
919ce03da6 Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
llvm-svn: 40578
2007-07-29 01:24:57 +00:00
Christopher Lamb
4120412f3e Add register info needed to use subreg sets on X86.
llvm-svn: 40572
2007-07-28 19:03:30 +00:00
Duncan Sands
35a77d857b Trampoline codegen support for X86-32.
llvm-svn: 40566
2007-07-27 20:02:49 +00:00
Dan Gohman
0252aa07ee Re-apply 40504, but with a fix for the segfault it caused in oggenc:
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
2007-07-27 17:16:43 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is
still under discussion.

llvm-svn: 40549
2007-07-27 12:58:54 +00:00
Evan Cheng
cb8f08ebca Reverting 40504 for now. It's breaking oggenc.
llvm-svn: 40547
2007-07-27 01:37:47 +00:00
Evan Cheng
ffa8cbd22b Make sure epilogue esp adjustment is placed before any terminator and pop instructions.
llvm-svn: 40538
2007-07-26 17:45:41 +00:00
Evan Cheng
ea037bffd2 Don't pollute the meaning of isUnpredicatedTerminator.
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
Evan Cheng
9802b13b38 Minor bug.
llvm-svn: 40535
2007-07-26 17:02:45 +00:00
Dan Gohman
d3a062f01b In the .loc directive, print the fields as "debug" fields, so they
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
2007-07-26 15:24:15 +00:00
Dan Gohman
1bfc3f0d09 Fix a whitespace difference between CMPSSrr and CMPSDrr.
llvm-svn: 40528
2007-07-26 15:11:50 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Evan Cheng
413d222576 Same goes for constantpool, etc.
llvm-svn: 40517
2007-07-26 07:35:15 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350
llvm-svn: 40516
2007-07-26 07:34:40 +00:00
Dan Gohman
513dcba4f8 Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
2007-07-26 00:31:09 +00:00
Evan Cheng
9588231d34 Mac OS X x86-64 lower 4G address is not available.
llvm-svn: 40502
2007-07-25 23:41:36 +00:00