1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-29 23:12:55 +01:00
Commit Graph

5272 Commits

Author SHA1 Message Date
Chris Lattner
758878175b Align vectors to the size in bytes, not bits.
llvm-svn: 27376
2006-04-03 19:28:50 +00:00
Chris Lattner
c65511b05c Add the full set of min/max instructions
llvm-svn: 27372
2006-04-03 15:58:28 +00:00
Andrew Lenharth
4760eaae91 support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4
llvm-svn: 27370
2006-04-03 04:19:17 +00:00
Andrew Lenharth
af4a638eab mul by const conversion sequences. more coming soon
llvm-svn: 27368
2006-04-03 03:18:59 +00:00
Andrew Lenharth
4c950de4c1 This makes McCat/12-IOtest go 8x faster or so
llvm-svn: 27363
2006-04-02 21:08:39 +00:00
Andrew Lenharth
067eaad4d9 This will be needed soon
llvm-svn: 27362
2006-04-02 20:13:57 +00:00
Chris Lattner
fa82c33ae7 add a note
llvm-svn: 27360
2006-04-02 07:20:00 +00:00
Chris Lattner
8ba4723c74 Inform the dag combiner that the predicate compares only return a low bit.
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
Chris Lattner
0b4f7786d2 relax assertion
llvm-svn: 27358
2006-04-02 06:19:46 +00:00
Chris Lattner
6433904644 Allow targets to compute masked bits for intrinsics.
llvm-svn: 27357
2006-04-02 06:15:09 +00:00
Chris Lattner
8967316b8c Remove done item
llvm-svn: 27351
2006-04-02 05:28:54 +00:00
Chris Lattner
9c24ec6de5 add a note
llvm-svn: 27348
2006-04-02 03:59:11 +00:00
Chris Lattner
2a24d68439 New note
llvm-svn: 27337
2006-04-02 01:47:20 +00:00
Chris Lattner
da4217646a Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335
2006-04-02 00:43:36 +00:00
Chris Lattner
38318b2706 Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
llvm-svn: 27331
2006-04-01 22:41:47 +00:00
Chris Lattner
894231e63e ADd a note
llvm-svn: 27324
2006-04-01 04:08:29 +00:00
Chris Lattner
32bb17a5f3 Shrinkify some more intrinsic definitions.
llvm-svn: 27322
2006-03-31 22:41:56 +00:00
Evan Cheng
403cd8f787 An entry about packed type alignments.
llvm-svn: 27321
2006-03-31 22:35:14 +00:00
Chris Lattner
12e9ce7104 Pull operand asm string into base class, shrinkifying intrinsic definitions.
No functionality change.

llvm-svn: 27320
2006-03-31 22:34:05 +00:00
Evan Cheng
fc0a2ac06e TargetData.cpp::getTypeInfo() was returning alignment of element type as the
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).

llvm-svn: 27319
2006-03-31 22:33:42 +00:00
Chris Lattner
3d6e5f8a05 Fix 80 column violations :)
llvm-svn: 27315
2006-03-31 21:57:36 +00:00
Evan Cheng
4623ebd3d0 Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314
2006-03-31 21:55:24 +00:00
Evan Cheng
fb980688f1 Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
llvm-svn: 27310
2006-03-31 21:29:33 +00:00
Chris Lattner
d66dd2a4ee fix a pasto
llvm-svn: 27308
2006-03-31 21:19:06 +00:00
Chris Lattner
28219f34bc Add vperm support for all datatypes
llvm-svn: 27307
2006-03-31 20:00:35 +00:00
Chris Lattner
336d6646ab Rearrange code a bit
llvm-svn: 27306
2006-03-31 19:52:36 +00:00
Chris Lattner
786f782398 Add, sub and shuffle are legal for all vector types
llvm-svn: 27305
2006-03-31 19:48:58 +00:00
Evan Cheng
7b9a0c6d7a Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.

llvm-svn: 27304
2006-03-31 19:22:53 +00:00
Evan Cheng
5da48f30bb Add vector_extract and vector_insert nodes.
llvm-svn: 27303
2006-03-31 19:21:16 +00:00
Chris Lattner
d27ced882b add a note
llvm-svn: 27302
2006-03-31 19:00:22 +00:00
Chris Lattner
e3774da014 note to self: *save* file, then check it in
llvm-svn: 27291
2006-03-31 06:04:53 +00:00
Chris Lattner
95d358dbdb Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

llvm-svn: 27290
2006-03-31 06:02:07 +00:00
Chris Lattner
560f734320 compactify some more instruction definitions
llvm-svn: 27288
2006-03-31 05:38:32 +00:00
Chris Lattner
2c3d6bdb55 Compactify comparisons.
llvm-svn: 27287
2006-03-31 05:32:57 +00:00
Chris Lattner
e330741a6c Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes.

llvm-svn: 27285
2006-03-31 05:13:27 +00:00
Chris Lattner
a7a7c035b3 These are done
llvm-svn: 27284
2006-03-31 04:53:21 +00:00
Chris Lattner
00921c047c Was returning the wrong type.
llvm-svn: 27277
2006-03-31 01:50:09 +00:00
Chris Lattner
a31d719e0a Mark INSERT_VECTOR_ELT as expand
llvm-svn: 27276
2006-03-31 01:48:55 +00:00
Evan Cheng
4ca9bbc1bb Expand all INSERT_VECTOR_ELT (obviously bad) for now.
llvm-svn: 27275
2006-03-31 01:30:39 +00:00
Chris Lattner
8e0dfe133c Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.

llvm-svn: 27273
2006-03-31 00:46:36 +00:00
Evan Cheng
5d9fc9fdd0 Typo
llvm-svn: 27272
2006-03-31 00:33:57 +00:00
Evan Cheng
c55052da81 Ok for vector_shuffle mask to contain undef elements.
llvm-svn: 27271
2006-03-31 00:30:29 +00:00
Chris Lattner
7f48037ef1 Implement TargetLowering::getPackedTypeBreakdown
llvm-svn: 27270
2006-03-31 00:28:56 +00:00
Chris Lattner
87d3a2e045 Add the rest of the vmul instructions and the vmulsum* instructions.
llvm-svn: 27268
2006-03-30 23:39:06 +00:00
Chris Lattner
22b7e551f1 Use a new tblgen feature to significantly shrinkify instruction definitions that
directly correspond to intrinsics.

llvm-svn: 27266
2006-03-30 23:21:27 +00:00
Chris Lattner
6aca6013d2 Add a bunch of new instructions for intrinsics.
llvm-svn: 27265
2006-03-30 23:07:36 +00:00
Evan Cheng
d3c692650f Make sure all possible shuffles are matched.
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
2006-03-30 19:54:57 +00:00
Evan Cheng
4150ec59a3 More logical ops patterns
llvm-svn: 27257
2006-03-30 07:33:32 +00:00
Evan Cheng
57d481a78a Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics
llvm-svn: 27256
2006-03-30 06:21:22 +00:00
Evan Cheng
82d2a6910f Add 128-bit pmovmskb intrinsic support.
llvm-svn: 27255
2006-03-30 00:33:26 +00:00
Evan Cheng
9ebe75e915 Change SSE pack operation definitions to fit what the intrinsics expected.
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
2006-03-29 23:53:14 +00:00
Evan Cheng
7bc3bc8246 - Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
2006-03-29 23:07:14 +00:00
Evan Cheng
d0d3eade59 Need to special case splat after all. Make the second operand of splat
vector_shuffle undef.

llvm-svn: 27250
2006-03-29 19:02:40 +00:00
Evan Cheng
e7701928bb Floating point logical operation patterns should match bit_convert. Or else
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
2006-03-29 18:47:40 +00:00
Evan Cheng
02b5de9b3e - More shuffle related bug fixes.
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
2006-03-29 03:04:49 +00:00
Evan Cheng
6e8b924416 Another entry about shuffles.
llvm-svn: 27245
2006-03-29 03:03:46 +00:00
Evan Cheng
5194a37602 - Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes.

llvm-svn: 27244
2006-03-29 01:30:51 +00:00
Chris Lattner
1a773f8f18 add a note
llvm-svn: 27243
2006-03-29 00:24:13 +00:00
Evan Cheng
e7a50a5851 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
2006-03-28 23:51:43 +00:00
Evan Cheng
178e36174a Fixing buggy code.
llvm-svn: 27239
2006-03-28 23:41:33 +00:00
Chris Lattner
93559450b8 add a note
llvm-svn: 27227
2006-03-28 18:56:23 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly.
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Jim Laskey
fa6dfa9212 Added missing paren on behalf of Ramana Radhakrishnan.
llvm-svn: 27223
2006-03-28 10:17:11 +00:00
Evan Cheng
0305cec743 Missed X86::isUNPCKHMask
llvm-svn: 27222
2006-03-28 08:27:15 +00:00
Evan Cheng
7b7954f53f movlps and movlpd should be modeled as two address code.
llvm-svn: 27221
2006-03-28 07:01:28 +00:00
Evan Cheng
a96380ba3f Update
llvm-svn: 27220
2006-03-28 06:55:45 +00:00
Evan Cheng
9f0e244187 Typo
llvm-svn: 27219
2006-03-28 06:53:49 +00:00
Evan Cheng
fb4b2bfc7d * Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
* Bug fixes.

llvm-svn: 27218
2006-03-28 06:50:32 +00:00
Nate Begeman
d432d66cc8 Fix a couple typos
llvm-svn: 27216
2006-03-28 04:18:18 +00:00
Nate Begeman
5a82c8ccbd Add a few more altivec intrinsics
llvm-svn: 27215
2006-03-28 04:15:58 +00:00
Evan Cheng
ca067debe3 Added a couple of entries about movhps and movlhps.
llvm-svn: 27212
2006-03-28 02:49:12 +00:00
Evan Cheng
9accac09cd All unpack cases are now being handled.
llvm-svn: 27211
2006-03-28 02:44:05 +00:00
Evan Cheng
4d554dae17 - Clean up / consoladate various shuffle masks.
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210
2006-03-28 02:43:26 +00:00
Chris Lattner
a570305421 implement a bunch more intrinsics.
llvm-svn: 27209
2006-03-28 02:29:37 +00:00
Chris Lattner
ac98e20cc9 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
same thing and we have a dag node for the former.

llvm-svn: 27205
2006-03-28 01:43:22 +00:00
Chris Lattner
d5da541d42 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
Evan Cheng
d8d7ec47bd Model unpack lower and interleave as vector_shuffle so we can lower the
intrinsics as such.

llvm-svn: 27200
2006-03-28 00:39:58 +00:00
Jim Laskey
8688957c53 Translate llvm target registers to dwarf register numbers properly.
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
Chris Lattner
b64eb6593a unbreak the build
llvm-svn: 27174
2006-03-27 16:52:45 +00:00
Chris Lattner
dab8425129 Add a bunch of notes from my journey thus far.
llvm-svn: 27170
2006-03-27 07:41:00 +00:00
Chris Lattner
f1d6a9483f Split out altivec notes into their own README
llvm-svn: 27168
2006-03-27 07:04:16 +00:00
Evan Cheng
0865274fa5 Use pcmpeq to generate vector of all ones.
llvm-svn: 27167
2006-03-27 07:00:16 +00:00
Evan Cheng
2a36326bb0 Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.
llvm-svn: 27166
2006-03-27 06:59:32 +00:00
Chris Lattner
4b0fc38fe7 Fix the JIT encoding of VSEL
llvm-svn: 27160
2006-03-27 03:34:17 +00:00
Chris Lattner
b5efa3e0f5 Fix the JIT encoding of VSPLTI*
llvm-svn: 27159
2006-03-27 03:28:57 +00:00
Nate Begeman
3d518334b9 SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156
2006-03-27 01:32:24 +00:00
Chris Lattner
03ad35fd49 add vsel
llvm-svn: 27153
2006-03-26 22:38:43 +00:00
Nate Begeman
507e293848 Readme note
llvm-svn: 27152
2006-03-26 19:19:27 +00:00
Chris Lattner
65a455b060 Codegen vector predicate compares.
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
Evan Cheng
1dfbede1d1 Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
llvm-svn: 27150
2006-03-26 09:53:12 +00:00
Evan Cheng
b17bbf8ccb Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
llvm-svn: 27149
2006-03-26 09:52:32 +00:00
Evan Cheng
5809827989 Add immAllZerosV helper
llvm-svn: 27148
2006-03-26 09:51:39 +00:00
Chris Lattner
f0c36b99e6 Add all of the altivec comparison instructions. Add patterns for the
non-predicate altivec compare intrinsics.

llvm-svn: 27143
2006-03-26 04:57:17 +00:00
Chris Lattner
4e0a78ea30 Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
intrinsics.

llvm-svn: 27142
2006-03-26 02:39:02 +00:00
Chris Lattner
d33ef7a1bc implement the vsldoi intrinsic.
llvm-svn: 27139
2006-03-26 00:41:48 +00:00
Chris Lattner
7d557e00f3 fix the pattern for vandc, it's NOT vnand
llvm-svn: 27136
2006-03-25 23:10:40 +00:00
Chris Lattner
88a0c65463 add patterns for VANDC/VNOR, implementing
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC

llvm-svn: 27135
2006-03-25 23:05:29 +00:00
Chris Lattner
f83db1efe6 add a vnot helper node for matching 'not' on vectors
llvm-svn: 27132
2006-03-25 23:00:08 +00:00
Chris Lattner
f80b39f9b1 Add some logical operations
llvm-svn: 27127
2006-03-25 22:16:05 +00:00
Evan Cheng
875c895b0f Added missing (any_extend (load ...)) patterns.
llvm-svn: 27120
2006-03-25 09:45:48 +00:00
Evan Cheng
e5807f6b47 Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.

llvm-svn: 27119
2006-03-25 09:37:23 +00:00
Chris Lattner
d2823658b4 implement a bunch of intrinsics
llvm-svn: 27118
2006-03-25 08:01:02 +00:00
Chris Lattner
cb5f9269a9 Move all Altivec stuff out into a new PPCInstrAltivec.td file.
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

llvm-svn: 27117
2006-03-25 07:51:43 +00:00
Chris Lattner
57064915a6 Add some basic patterns for other datatypes
llvm-svn: 27116
2006-03-25 07:39:07 +00:00
Chris Lattner
7f5fba9c67 add all supported formats to the vector register file
llvm-svn: 27115
2006-03-25 07:36:56 +00:00
Chris Lattner
2fa3a6c436 Add support for __builtin_altivec_vnmsubfp /vmaddfp
llvm-svn: 27112
2006-03-25 07:05:55 +00:00
Chris Lattner
e199d55073 #include Intrinsics.h into all dag isels
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
Chris Lattner
0899b16b2d Codegen things like:
<int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

llvm-svn: 27106
2006-03-25 06:12:06 +00:00
Evan Cheng
8601147e68 Added SSE cachebility ops
llvm-svn: 27103
2006-03-25 06:03:26 +00:00
Evan Cheng
cad90504fe Instruction encoding bug
llvm-svn: 27102
2006-03-25 06:00:03 +00:00
Chris Lattner
b0e8c6dd7f Add new intrinsic node definitions for tblgen use
llvm-svn: 27100
2006-03-25 02:29:35 +00:00
Evan Cheng
234090b386 Added 128-bit packed integer subtraction.
llvm-svn: 27096
2006-03-25 01:33:37 +00:00
Evan Cheng
b280b34497 Added CVTTPS2PI.
llvm-svn: 27095
2006-03-25 01:31:59 +00:00
Evan Cheng
041c9c534b Added CVTSS2SI.
llvm-svn: 27094
2006-03-25 01:00:18 +00:00
Evan Cheng
bdb85b387f Support for scalar to vector with zero extension.
llvm-svn: 27091
2006-03-24 23:15:12 +00:00
Jim Laskey
37a8c245ce D'oh - should be even numbered.
llvm-svn: 27088
2006-03-24 22:48:02 +00:00
Evan Cheng
33dad39b46 Added LDMXCSR
llvm-svn: 27087
2006-03-24 22:28:37 +00:00
Chris Lattner
2d08e8aee1 plug the intrinsics into the patterns for movmsk*
llvm-svn: 27083
2006-03-24 21:49:18 +00:00
Jim Laskey
1716e53341 Add dwarf register numbering to register data.
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
Jim Laskey
d577317f38 Add support for dwarf register numbering.
llvm-svn: 27080
2006-03-24 21:13:21 +00:00
Chris Lattner
8840036091 add another note
llvm-svn: 27077
2006-03-24 20:04:27 +00:00
Chris Lattner
045f6bf0ef add a note
llvm-svn: 27076
2006-03-24 19:59:17 +00:00
Chris Lattner
b979b51e39 Shuffle some includes around
llvm-svn: 27073
2006-03-24 18:52:35 +00:00
Chris Lattner
8e14f3544b expose intrinsic info to the targets.
llvm-svn: 27070
2006-03-24 18:44:11 +00:00
Chris Lattner
21abff3712 Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
llvm-svn: 27069
2006-03-24 18:24:43 +00:00
Chris Lattner
3133dafd4b Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

llvm-svn: 27068
2006-03-24 17:58:06 +00:00
Jim Laskey
06c78bb995 Clean up some commentary.
llvm-svn: 27064
2006-03-24 10:00:56 +00:00
Chris Lattner
303dc30593 Disable the i32->float G5 optimization. It is unsafe, as documented in the
comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.

llvm-svn: 27060
2006-03-24 07:53:47 +00:00
Chris Lattner
ba4966c16c add support for using vxor to build zero vectors. This implements
Regression/CodeGen/PowerPC/vec_zero.ll

llvm-svn: 27059
2006-03-24 07:48:08 +00:00
Evan Cheng
d58d54cf3e Handle BUILD_VECTOR with all zero elements.
llvm-svn: 27056
2006-03-24 07:29:27 +00:00
Chris Lattner
ace2d0d227 Gabor points out that we can't spell. :)
llvm-svn: 27049
2006-03-24 07:12:19 +00:00
Evan Cheng
8507228441 All v2f64 shuffle cases can be handled.
llvm-svn: 27044
2006-03-24 06:40:32 +00:00
Evan Cheng
3028b04057 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
llvm-svn: 27040
2006-03-24 02:58:06 +00:00
Evan Cheng
184c4b937e A new entry
llvm-svn: 27039
2006-03-24 02:57:03 +00:00
Reid Spencer
845084b469 Ignore the burg output files.
llvm-svn: 27033
2006-03-24 02:21:35 +00:00
Evan Cheng
68410804f0 Handle more shuffle cases with SHUFP* instructions.
llvm-svn: 27024
2006-03-24 01:18:28 +00:00
Evan Cheng
7528344998 Typo
llvm-svn: 27008
2006-03-23 23:24:51 +00:00
Chris Lattner
2e5162fa6e add a note
llvm-svn: 27000
2006-03-23 21:28:44 +00:00
Evan Cheng
daa75ed684 Typo
llvm-svn: 26997
2006-03-23 20:26:04 +00:00
Chris Lattner
974982c89c Add PPC vector bit-convert support
llvm-svn: 26995
2006-03-23 19:54:27 +00:00
Jim Laskey
cec9c18c62 Add support to locate local variables in frames (early version.)
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
Jim Laskey
f3cc740d75 Change interface to DwarfWriter.
llvm-svn: 26991
2006-03-23 18:09:44 +00:00
Jim Laskey
f47cb47216 Modify how CBE handles #lines.
llvm-svn: 26990
2006-03-23 18:08:29 +00:00
Chris Lattner
ec3f1b5cd1 Fix the encodings of these new instructions, hopefully fixing the JIT
failures from last night

llvm-svn: 26981
2006-03-23 16:13:50 +00:00
Evan Cheng
a6dc6e535d Following icc's lead: use movdqa to load / store 128-bit integer vectors
llvm-svn: 26980
2006-03-23 07:44:07 +00:00
Chris Lattner
89e0790edb Eliminate IntrinsicLowering from TargetMachine.
Make the CBE and V9 backends create their own, since they're the only ones that use it.

llvm-svn: 26974
2006-03-23 05:43:16 +00:00
Chris Lattner
3d5ca510c9 remove always-null IntrinsicLowering argument.
llvm-svn: 26971
2006-03-23 05:28:02 +00:00
Evan Cheng
c1fe87ea8b Add v4i32 <-> v4f32 bitconvert patterns.
llvm-svn: 26969
2006-03-23 02:36:37 +00:00
Evan Cheng
5f7cf963db Add 128-bit integer vector load and add (for testing).
llvm-svn: 26967
2006-03-23 01:57:24 +00:00
Nate Begeman
0ec15cd042 Add support for 8 bit immediates with 16/32 bit cmp instructions
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
Evan Cheng
54215cd1ea Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.

llvm-svn: 26964
2006-03-22 22:07:06 +00:00
Evan Cheng
56b67b2c4f SHUFP* are two address code.
llvm-svn: 26959
2006-03-22 20:08:18 +00:00
Evan Cheng
7cb4e14749 Some clean up.
llvm-svn: 26957
2006-03-22 19:22:18 +00:00
Evan Cheng
ae6a39ea92 - Supposely movlhps is faster / better than unpcklpd.
- Don't forget pshufd is only available with sse2.

llvm-svn: 26956
2006-03-22 19:16:21 +00:00
Evan Cheng
cff38e19c3 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
2006-03-22 08:01:21 +00:00
Chris Lattner
64be951e06 add a note
llvm-svn: 26950
2006-03-22 07:33:46 +00:00
Evan Cheng
25440d19b1 Fix PSHUF* and SHUF* jit code emission problems
llvm-svn: 26949
2006-03-22 07:10:28 +00:00
Chris Lattner
5141ebb2c4 This has been implemented. Tweak it into another note
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
Chris Lattner
f84f3bf95b When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943
2006-03-22 05:30:33 +00:00
Chris Lattner
cfbce5186a Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

llvm-svn: 26942
2006-03-22 05:26:03 +00:00
Chris Lattner
1554bf155e fix a warning
llvm-svn: 26941
2006-03-22 04:18:34 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support.
llvm-svn: 26940
2006-03-22 02:53:00 +00:00
Evan Cheng
b6c46ed8c9 Add a couple more pseudo instructions.
llvm-svn: 26939
2006-03-22 02:52:03 +00:00
Chris Lattner
2e606dc60f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
Evan Cheng
7c8d7bc4b3 Didn't mean to check this in. No MMX support yet.
llvm-svn: 26933
2006-03-21 23:04:23 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers.
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
2006-03-21 23:01:21 +00:00
Chris Lattner
31a93c7740 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
Chris Lattner
140be98ab8 Don't emit pseudo instructions!
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
Nate Begeman
4bd73df4bd Update readme
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
Chris Lattner
414fed4108 Print absolute memory references like this:
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.

llvm-svn: 26922
2006-03-21 17:21:13 +00:00
Evan Cheng
a56ed39464 Combine 2 entries
llvm-svn: 26921
2006-03-21 07:18:26 +00:00
Evan Cheng
f8d8d45ff8 Add a note about x86 register coallescing
llvm-svn: 26920
2006-03-21 07:12:57 +00:00
Evan Cheng
6ec225863c - Remove scalar to vector pseudo ops. They are just wrong.
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
2006-03-21 07:09:35 +00:00
Chris Lattner
6417236c41 With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
Chris Lattner
acb2506622 When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
Chris Lattner
9e611a25c7 minor note
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support.
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
Evan Cheng
d90127aafd Junk unused vector register classes.
llvm-svn: 26910
2006-03-21 00:30:59 +00:00
Chris Lattner
cdc4657988 Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr

llvm-svn: 26908
2006-03-20 22:38:22 +00:00
Chris Lattner
a498dd25d9 remove dead variable
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
Chris Lattner
978628896b Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
figuring these out! :)

llvm-svn: 26904
2006-03-20 18:26:51 +00:00
Chris Lattner
5c994b8c63 reenable this hack, the tblgen version isn't quite ready
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
Chris Lattner
fb0e160aa5 Fix the pattern for VADDUWM, add i32 splat
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
Evan Cheng
57da1afbc8 Use tblgen'd VECTOR_SHUFFLE selection code.
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
Chris Lattner
dc3605efdb Add support for generating vspltw, instead of a vperm instruction with a
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.

llvm-svn: 26898
2006-03-20 06:51:10 +00:00
Chris Lattner
8faa2cf693 Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
Chris Lattner
4b7aa59bbc fix duplicate definition errors
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
Chris Lattner
09ede9ec9f Add a build_vector node
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
Chris Lattner
1cdeda1c5a Check in some intermediate code that adds a skeleton for matching vsplt*
instructions

llvm-svn: 26894
2006-03-20 06:15:45 +00:00
Evan Cheng
c63d434203 Move a few things around.
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
Chris Lattner
5892479894 add vector_shuffle
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
Chris Lattner
c230af9810 fix typo
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
Chris Lattner
bea056ecf2 add vsplat instructions, fix sched description for vperm
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
Chris Lattner
0e56cf0d94 Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*

llvm-svn: 26887
2006-03-20 01:53:53 +00:00
Chris Lattner
65e6e12dca Claim to have v16i8 for perm masks
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
Chris Lattner
6f502da274 add the vperm instruction
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
Chris Lattner
9a87d3e90d add a note with a testcase
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
Chris Lattner
ada41aad4d Add a note about the MUL -> FMADD vector bug.
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
Evan Cheng
cc1e38c242 Vector undef's
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
Chris Lattner
789570bafb Custom lower SCALAR_TO_VECTOR into lve*x.
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
Chris Lattner
80f9f7138a PPC doesn't have SCALAR_TO_VECTOR
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
Chris Lattner
89bc332152 add support for vector undef
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
Evan Cheng
9f00d55227 Remind us of exit value substitution
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
Evan Cheng
99327f9351 Turning on LSR by default
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
Evan Cheng
98b79bf7ec Remember which tests are hurt by LSR.
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
Chris Lattner
a9b4a2ab99 minor fixes
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
Chris Lattner
d3910ca755 notes
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
Chris Lattner
b46a4c28ad we don't use lmw/stmw. When we want them they are easy enough to add
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
Chris Lattner
1bd0aaf2b8 rename these nodes
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc.

llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Nate Begeman
793c8136ae Fix subfic to match subc by default instead of sub so that it is correctly
cost-modeled as producing a flag.  This fixes the test I just added for neg

llvm-svn: 26835
2006-03-17 22:41:37 +00:00
Evan Cheng
f4774c9091 Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files.
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Chris Lattner
647503bccc Disable x86 fastcc from passing args in registers
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
Chris Lattner
a71bc63ced Parameterize the number of integer arguments to pass in registers
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
Evan Cheng
1f5cb60f28 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
Evan Cheng
fc79bdafbe Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
ADD32ri8.

llvm-svn: 26816
2006-03-17 02:25:01 +00:00
Evan Cheng
d16fa97974 - Nuke 16-bit SBB instructions. We'll never use them.
- Nuke a bogus comment.

llvm-svn: 26815
2006-03-17 02:24:04 +00:00
Nate Begeman
42736d46b2 Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
2006-03-17 01:40:33 +00:00
Chris Lattner
87dbd49cbe remove dead variable
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
Evan Cheng
33055a8aba A new entry.
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
Nate Begeman
63c4456867 Notes on how to kill the eeevil brtwoway, and make ppc branch selector
more target independant, generate better code, and be less conservative.

llvm-svn: 26809
2006-03-16 22:37:48 +00:00
Chris Lattner
f2008cb73b Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
Chris Lattner
8a756c5171 add a note
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
Chris Lattner
57773fdac1 teach the ppc backend how to spill/reload vector regs
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
Chris Lattner
661ee5d3c1 add callee saved vector regs
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
Evan Cheng
0e1abe6e19 Bug fix: condition inverted.
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
Evan Cheng
cad75d9f0c Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.

llvm-svn: 26802
2006-03-16 21:47:42 +00:00
Chris Lattner
7f5361757b in functions that use a lot of callee saved regs, this can be more than
5 instructions away.

llvm-svn: 26801
2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1 Add support for copying registers. still needed: spilling and reloading them
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
Chris Lattner
eac8e98036 set TransformToType correctly for vector types.
llvm-svn: 26797
2006-03-16 19:50:01 +00:00
Nate Begeman
cbca1b3d14 Another case we could do better on.
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
Chris Lattner
b5d0896994 Save/restore VRSAVE once per function, not once per block.
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
Chris Lattner
4fd1599ab1 add support for the bitconvert node
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
Nate Begeman
e371cb595a Update scheduling info for vrsave instruction
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
Chris Lattner
9df7eb4071 add a note
llvm-svn: 26762
2006-03-14 19:31:24 +00:00
Chris Lattner
392087f5bd Fix an off by one error that caused PPC LLC failures last night.
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
Chris Lattner
80c5fabe4e transformation implemented
llvm-svn: 26754
2006-03-14 06:57:34 +00:00
Evan Cheng
ae7469b2c5 PPC LSR pass should use target lowering hooks.
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this.
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
Evan Cheng
99e87e9147 Update
llvm-svn: 26741
2006-03-13 23:19:10 +00:00
Evan Cheng
ed013bd937 Add LSR hooks.
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
Chris Lattner
d5ecfd83f1 Handle builtins that directly correspond to GCC builtins.
llvm-svn: 26737
2006-03-13 23:09:05 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
2006-03-13 21:52:10 +00:00
Jim Laskey
c741139c24 Handle the removal of the debug chain.
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
Chris Lattner
ea1453c3dc remove two implemented items
llvm-svn: 26728
2006-03-13 06:52:22 +00:00
Chris Lattner
1782f3971d I can't convince myself that this is safe, remove the recursive call.
llvm-svn: 26725
2006-03-13 06:42:16 +00:00
Chris Lattner
3aff8e6acf Fix a couple of bugs that broke the alpha tester build
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
Chris Lattner
9898674f99 Handle cracked instructions in dispatch group formation.
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
Chris Lattner
ba10d4e4ab Mark instructions that are cracked by the PPC970 decoder as such.
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29 Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
2006-03-12 09:13:49 +00:00
Chris Lattner
19b93158c1 blr is a branch too
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
Chris Lattner
916761949b add an example
llvm-svn: 26709
2006-03-11 20:20:40 +00:00
Chris Lattner
115b1be710 add a note
llvm-svn: 26708
2006-03-11 20:17:08 +00:00
Chris Lattner
2370965e55 teach the JIT to encode vector registers
llvm-svn: 26697
2006-03-10 20:19:50 +00:00
Evan Cheng
471bd00cb5 Add option -enable-x86-lsr to enable x86 loop strength reduction pass.
llvm-svn: 26665
2006-03-09 21:51:28 +00:00
Chris Lattner
c08825d684 add a note
llvm-svn: 26661
2006-03-09 20:13:21 +00:00
Andrew Lenharth
bbf38867f2 these are copies too
llvm-svn: 26653
2006-03-09 18:18:51 +00:00
Chris Lattner
e93eeb189f remove some now-dead code
llvm-svn: 26652
2006-03-09 18:07:49 +00:00
Andrew Lenharth
f124519fc8 fcopysign for mixed mode
llvm-svn: 26651
2006-03-09 17:56:33 +00:00
Andrew Lenharth
2d36f9d389 relax fcopysign
llvm-svn: 26649
2006-03-09 17:47:22 +00:00
Andrew Lenharth
e08d165146 alpha and llvm have different oppinions on which arg is the sign bit
llvm-svn: 26647
2006-03-09 17:41:50 +00:00
Andrew Lenharth
25de2846c5 Alpha Scheduling classes
llvm-svn: 26643
2006-03-09 17:16:45 +00:00
Andrew Lenharth
c180d749a2 fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
llvm-svn: 26641
2006-03-09 14:58:25 +00:00
Andrew Lenharth
78af2795b3 fcopysign support
llvm-svn: 26640
2006-03-09 14:57:36 +00:00
Chris Lattner
125881e75b Add support for 'special' llvm globals like debug info and static ctors/dtors.
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
Chris Lattner
57acce1443 a couple of miscellaneous things.
llvm-svn: 26625
2006-03-09 01:39:46 +00:00
Jim Laskey
84a3db4538 Add #line support for CBE.
llvm-svn: 26621
2006-03-08 19:31:15 +00:00
Duraid Madina
a3c5cd22e1 doo de doo
llvm-svn: 26614
2006-03-08 06:18:46 +00:00
Chris Lattner
3f23d22d3f Change the interface for getting a target HazardRecognizer to be more clean.
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
Chris Lattner
24aa564456 add a note
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
Evan Cheng
d73d06f052 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
Evan Cheng
a3e0a7f652 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
and variable value.
Similarly for memcpy.

llvm-svn: 26603
2006-03-07 23:29:39 +00:00
Chris Lattner
4c47b8cd69 Two things:
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
   compiled with the new CFE.

llvm-svn: 26602
2006-03-07 22:58:23 +00:00
Jim Laskey
91d5ce2531 Use "llvm.metadata" section for debug globals. Filter out these globals in the
asm printer.

llvm-svn: 26599
2006-03-07 22:00:35 +00:00
Chris Lattner
27f87a6955 add another missing store.
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
Chris Lattner
dfdeec73bc add a couple more load/store instrs, add a newline to the end of file.
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
Nate Begeman
a8bc3c0c3c This kinda sorta implements "things that have to lead a dispatch group".
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
Chris Lattner
842436586c add some new instructions to the classifier. With this, we correctly insert
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).

llvm-svn: 26590
2006-03-07 07:14:55 +00:00
Chris Lattner
0cd4bd574c add some comments that describe what we model
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
Chris Lattner
4cd6cd499d Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes

llvm-svn: 26587
2006-03-07 06:32:48 +00:00
Chris Lattner
ae34bbf56b add a note
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
Chris Lattner
174768dde0 add a note
llvm-svn: 26583
2006-03-07 02:46:26 +00:00
Evan Cheng
03940bfcfe - Emit subsections_via_symbols for Darwin.
- Conditionalize Dwarf debugging output (Darwin only for now).

llvm-svn: 26582
2006-03-07 02:23:26 +00:00
Evan Cheng
2327759419 Enable Dwarf debugging info.
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner
af44ead7f3 implement TII::insertNoop
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
Chris Lattner
4957693551 add a note
llvm-svn: 26549
2006-03-05 20:00:08 +00:00
Chris Lattner
f8cbc8c4ea Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
we want to canonicalize the other way.

llvm-svn: 26547
2006-03-05 19:52:57 +00:00
Chris Lattner
6b0947c277 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
implement copysign as a native op if they have it.

llvm-svn: 26541
2006-03-05 05:08:37 +00:00
Chris Lattner
55fbd49ca9 add a note for something evan noticed
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
Chris Lattner
7d2423c91f Implemented.
llvm-svn: 26536
2006-03-04 23:33:44 +00:00
Chris Lattner
35dbbc5676 Add a note
llvm-svn: 26523
2006-03-04 08:44:51 +00:00
Evan Cheng
65b5c2c680 Add an entry
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
Evan Cheng
2b45c57663 MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
rep/stos and rep/mov if the count is not a constant. We could do
  rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.

Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.

llvm-svn: 26517
2006-03-04 02:48:56 +00:00
Chris Lattner
de8c7d8ae2 add a note
llvm-svn: 26513
2006-03-04 01:19:34 +00:00
Evan Cheng
f2a0107221 Typo
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
Evan Cheng
0c445855f2 Number of NodeTypes now exceeds 128.
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
Chris Lattner
af9919716a Split the valuetypes out of Target.td into ValueTypes.td
llvm-svn: 26490
2006-03-03 01:55:26 +00:00
Chris Lattner
999aa36a04 remove the read/write port/io intrinsics.
llvm-svn: 26479
2006-03-03 00:19:58 +00:00