Try to improve method comments a little.
Get rid of some excess whitespace; put braces on previous line when possible.
Add stub for method to verify the work of saveState().
llvm-svn: 9385
PhyRegAlloc.cpp:
Don't include TargetMachine.h or TargetRegInfo.h, because these are provided
by PhyRegAlloc.h.
Merge class RegisterAllocator into class PhyRegAlloc.
Simplify & move ctor, dtor to PhyRegAlloc.h.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
MarkAllocatedRegs() becomes a member method, with fewer args.
PhyRegAlloc.h:
Include Pass.h, TargetMachine.h and TargetRegInfo.h. Don't declare
TargetRegInfo forward.
Give AddedInstrns the obvious clear() method.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
Add prototype for markAllocatedRegs().
Remove unused inline void constructLiveRanges().
llvm-svn: 8641
we no longer need to find the live-before set of the delayed
branch since that set is now included the live-before/after
set of the instructions in each delay slot. Just assert that instead.
llvm-svn: 7796
spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).
2. Bug fix: Delete the delay slot instr, not the branch instr, when
moving delay slot instr. out!!!!
3. Move code to insert caller-saves moved here from SparcRegInfo:
it is now machine-independent.
llvm-svn: 7389
info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
llvm-svn: 7329
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
llvm-svn: 7152
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341
overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
bitvector. Sped up LLC a little less than 10% in a debug build!
llvm-svn: 4261
