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Commit Graph

154129 Commits

Author SHA1 Message Date
Reid Kleckner
96e5ac119a [cmake] Fix a variable shadowing bug
llvm-svn: 313331
2017-09-15 01:18:46 +00:00
Reid Kleckner
4ae1df5b81 [codeview] Use a type index of zero for static method "this" types
Otherwise VS won't show anything in the autos or watch window of static
methods.

llvm-svn: 313329
2017-09-15 00:59:07 +00:00
Zachary Turner
d1ff5541e1 [lit] Revert "Add a lit.llvm module that all llvm projects can use"
This is breaking due to some changes I forgot to merge in, so I'm
temporarily reverting them until I can re-test that this works.

llvm-svn: 313328
2017-09-15 00:56:08 +00:00
Zachary Turner
06c0db4fd1 [lit] Remove some code that I forgot to remove.
llvm-svn: 313326
2017-09-15 00:43:38 +00:00
Zachary Turner
a0b8a1442a [lit] Add a lit.llvm module that all test suites can use.
To further reduce duplicate code, this patch introduces a module
that configs can simply import and get access to a lot of useful
functionality such as setting up paths, adding features that are
useful across all projects, and other utility-type functions.

For now this only updates llvm's suite to use this new library,
but subsequent patches will update other projects.

Differential Revision: https://reviews.llvm.org/D37778

llvm-svn: 313325
2017-09-15 00:34:00 +00:00
Alina Sbirlea
bf65988660 Refactor collectChildrenInLoop to LoopUtils [NFC]
Summary: Move to LoopUtils method that collects all children of a node inside a loop.

Reviewers: majnemer, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37870

llvm-svn: 313322
2017-09-15 00:04:16 +00:00
Sam Clegg
98d7dfcbb9 [WebAssembly] Use a separate wasm data segment for each global symbol
This is stepping stone towards honoring -fdata-sections
and letting the assembler decide how many wasm data
segments to create.

Differential Revision: https://reviews.llvm.org/D37834

llvm-svn: 313313
2017-09-14 23:07:53 +00:00
Eric Beckmann
c0f1f5876a Fix bug 34608 by moving private header out of public header.
WindowsManifestMerger.h should not include llvm/Config/config.h, since it is private.  The include has been moved to the source instead.

Summary:
The checksums had already been placed in the IR, this patch allows
MCCodeView to actually write it out to an MCStreamer.

Move private config.h header dependency out of public header file.

Addresses Bug 34608

Subscribers: javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D37863

llvm-svn: 313312
2017-09-14 23:01:13 +00:00
Craig Topper
3bcc062cdc [X86] Remove an unnecessary SmallVector from LowerBUILD_VECTOR.
I think this may have existed to convert from SDUse to SDValue, but it doesn't look like its needed now.

llvm-svn: 313311
2017-09-14 22:47:59 +00:00
Jan Sjodin
43e732c065 Fix warnings in r313297.
llvm-svn: 313302
2017-09-14 21:49:52 +00:00
Zachary Turner
78d9ca9e25 [lit] Fix some windows line endings that snuck in.
llvm-svn: 313301
2017-09-14 21:32:13 +00:00
Matt Arsenault
a8560d8853 AMDGPU: Fix violating constant bus restriction
You can't use madmk/madmk if it already uses an SGPR input.

llvm-svn: 313298
2017-09-14 20:54:29 +00:00
Jan Sjodin
242b2dcd0b Add AddresSpace to PseudoSourceValue.
Differential Revision: https://reviews.llvm.org/D35089

llvm-svn: 313297
2017-09-14 20:53:51 +00:00
Krzysztof Parzyszek
97d598594a Subtarget support for parameterized register class information
Implement "checkFeatures" and emitting HW mode check code.

Differential Revision: https://reviews.llvm.org/D31959

llvm-svn: 313295
2017-09-14 20:44:20 +00:00
Guozhi Wei
3025ed18e5 [TargetTransformInfo] Detect 0 latency instructions
For instructions that unlikely generate machine instructions, they should also have 0 latency.

Differential Revision: https://reviews.llvm.org/D37833

llvm-svn: 313288
2017-09-14 19:20:02 +00:00
Benjamin Kramer
b6a866ac7b Remove usages of deprecated std::unary_function and std::binary_function.
These are removed in C++17. We still have some users of
unary_function::argument_type, so just spell that typedef out. No
functionality change intended.

Note that many of the argument types are actually wrong :)

llvm-svn: 313287
2017-09-14 18:33:25 +00:00
Matt Arsenault
f18ea9e4aa AMDGPU: Fix assert on alloca of array of struct
llvm-svn: 313282
2017-09-14 18:02:29 +00:00
Simon Dardis
cfabd99bf6 [bpf] Fix test to always use little endian.
r313055 broke the big endian buildbots as the CHECK lines contained little
endian data but -triple bpf uses the host endian.

llvm-svn: 313281
2017-09-14 17:55:50 +00:00
Jonas Devlieghere
df36b9b028 [test] Fix TestDWARFDieRangeInfoIntersects
Fixes heap buffer overflow triggered in DWARF verifier, detected by ASAN.

llvm-svn: 313280
2017-09-14 17:46:23 +00:00
Matt Arsenault
0a3745b2a6 AMDGPU: Stop modifying SP in call sequences
Because the stack growth direction and addressing is done
in the same direction, modifying SP at the beginning of the
call sequence was incorrect. If we had a stack passed argument,
we would end up skipping that number of bytes before pushing
arguments, leaving unused/inconsistent space.

The callee creates fixed stack objects in its frame, so
the space necessary for these is already logically allocated
in the callee, so we just let the callee increment SP if
it really requires it.

llvm-svn: 313279
2017-09-14 17:37:40 +00:00
Dehao Chen
c6dcd59361 Invoke GetInlineCost for legality check before inline functions in SampleProfileLoader.
Summary: SampleProfileLoader inlines hot functions if it is inlined in the profiled binary. However, the inline needs to be guarded by legality check, otherwise it could lead to correctness issues.

Reviewers: eraman, davidxl

Reviewed By: eraman

Subscribers: vitalybuka, sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D37779

llvm-svn: 313277
2017-09-14 17:29:56 +00:00
Simon Dardis
c8036cbb4c [mips] Implement the 'dext' aliases and it's disassembly alias.
The other members of the dext family of instructions (dextm, dextu) are
traditionally handled by the assembler selecting the right variant of
'dext' depending on the values of the position and size operands.

When these instructions are disassembled, rather than reporting the
actual instruction, an equivalent aliased form of 'dext' is generated
and is reported. This is to mimic the behaviour of binutils.

Reviewers: slthakur, nitesh.jain, atanasyan

Differential Revision: https://reviews.llvm.org/D34887

llvm-svn: 313276
2017-09-14 17:27:53 +00:00
Adrian Prantl
18cd6e29b7 Adapt more testcases for llvm-dwarfdump changes.
llvm-svn: 313275
2017-09-14 17:27:03 +00:00
Matt Arsenault
332360a091 AMDGPU: Make frame register caller preserved
Using SplitCSR for the frame register was very broken. Often
the copies in the prolog and epilog were optimized out, in addition
to them being inserted after the true prolog where the FP
was clobbered.

I have a hacky solution which works that continues to use
split CSR, but for now this is simpler and will get to working
programs.

llvm-svn: 313274
2017-09-14 17:14:57 +00:00
Krzysztof Parzyszek
5c9e9120f7 Silence warning about unused variable in release build
llvm-svn: 313273
2017-09-14 17:08:26 +00:00
Adrian Prantl
180de22eaf llvm-dwarfdump: support dumping static archives.
llvm-svn: 313272
2017-09-14 17:01:53 +00:00
Krzysztof Parzyszek
f817a9b5c3 TableGen support for parameterized register class information
This replaces TableGen's type inference to operate on parameterized
types instead of MVTs, and as a consequence, some interfaces have
changed:
- Uses of MVTs are replaced by ValueTypeByHwMode.
- EEVT::TypeSet is replaced by TypeSetByHwMode.

This affects the way that types and type sets are printed, and the
tests relying on that have been updated.

There are certain users of the inferred types outside of TableGen
itself, namely FastISel and GlobalISel. For those users, the way
that the types are accessed have changed. For typical scenarios,
these replacements can be used:
- TreePatternNode::getType(ResNo) -> getSimpleType(ResNo)
- TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo)
- TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false)

For more information, please refer to the review page.

Differential Revision: https://reviews.llvm.org/D31951

llvm-svn: 313271
2017-09-14 16:56:21 +00:00
Zachary Turner
2fadf8bf73 [lit] Force site configs to be run before source-tree configs
This patch simplifies LLVM's lit infrastructure by enforcing an ordering
that a site config is always run before a source-tree config.

A significant amount of the complexity from lit config files arises from
the fact that inside of a source-tree config file, we don't yet know if
the site config has been run.  However it is *always* required to run
a site config first, because it passes various variables down through
CMake that the main config depends on.  As a result, every config
file has to do a bunch of magic to try to reverse-engineer the location
of the site config file if they detect (heuristically) that the site
config file has not yet been run.

This patch solves the problem by emitting a mapping from source tree
config file to binary tree site config file in llvm-lit.py. Then, during
discovery when we find a config file, we check to see if we have a
target mapping for it, and if so we use that instead.

This mechanism is generic enough that it does not affect external users
of lit. They will just not have a config mapping defined, and everything
will work as normal.

On the other hand, for us it allows us to make many simplifications:

* We are guaranteed that a site config will be executed first
* Inside of a main config, we no longer have to assume that attributes
  might not be present and use getattr everywhere.
* We no longer have to pass parameters such as --param llvm_site_config=<path>
  on the command line.
* It is future-proof, meaning you don't have to edit llvm-lit.in to add
  support for new projects.
* All of the duplicated logic of trying various fallback mechanisms of
  finding a site config from the main config are now gone.

One potentially noteworthy thing that was required to implement this
change is that whereas the ninja check targets previously used the first
method to spawn lit, they now use the second. In particular, you can no
longer run lit.py against the source tree while specifying the various
`foo_site_config=<path>` parameters.  Instead, you need to run
llvm-lit.py.

Differential Revision: https://reviews.llvm.org/D37756

llvm-svn: 313270
2017-09-14 16:47:58 +00:00
Benjamin Kramer
004d2b7e9e [tblgen] Remove uses of std::ptr_fun, it's removed in C++17.
No functionality change intended.

llvm-svn: 313269
2017-09-14 16:30:31 +00:00
Krzysztof Parzyszek
0a6ba29aad [IfConversion] More simple, correct dead/kill liveness handling
Patch by Jesper Antonsson.

Differential Revision: https://reviews.llvm.org/D37611

llvm-svn: 313268
2017-09-14 15:53:11 +00:00
Simon Dardis
279ec81c7c [mips] Implement the 'dins' aliases.
Traditionally GAS has provided automatic selection between dins, dinsm and
dinsu. Binutils also disassembles all instructions in that family as 'dins'
rather than the actual instruction.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D34877

llvm-svn: 313267
2017-09-14 15:17:50 +00:00
Sanjay Patel
3e2b1fd515 [InstSimplify] fold sdiv/srem based on compare of dividend and divisor
This should bring signed div/rem analysis up to the same level as unsigned. 
We use icmp simplification to determine when the divisor is known greater than the dividend.

Each positive test is followed by a negative test to show that we're not overstepping the boundaries of the known bits.
There are extra tests for the signed-min-value special cases.

Alive proofs:
http://rise4fun.com/Alive/WI5

Differential Revision: https://reviews.llvm.org/D37713

llvm-svn: 313264
2017-09-14 14:59:07 +00:00
Chad Rosier
1ca614cedd Add newline to end of test file. NFC.
llvm-svn: 313263
2017-09-14 14:48:59 +00:00
Aleksandar Beserminji
22c7d9115b Test commit.
llvm-svn: 313262
2017-09-14 14:34:04 +00:00
Sanjay Patel
cb5ae7de4b [InstSimplify] clean up div/rem handling; NFCI
The idea to make an 'isDivZero' helper was suggested for the signed case in D37713:
https://reviews.llvm.org/D37713

This clean-up makes it clear that D37713 is just filling the gap for signed div/rem,
removes unnecessary code, and allows us to remove a bit of duplicated code from the
planned improvement in D37713.

llvm-svn: 313261
2017-09-14 14:09:11 +00:00
Simon Pilgrim
3395568d90 [X86] Regenerate test. NFCI.
llvm-svn: 313259
2017-09-14 13:00:27 +00:00
Simon Pilgrim
02d556f618 Regenerate test (broadcast comment). NFCI.
llvm-svn: 313258
2017-09-14 12:41:19 +00:00
Krzysztof Parzyszek
805df76dbe [Hexagon] Make getMemAccessSize return size in bytes
It used to return the actual field value from the instruction descriptor.
There is no reason for that, that value is not interesting in any way and
the specifics of its encoding in the descriptor should not be exposed.

llvm-svn: 313257
2017-09-14 12:06:40 +00:00
Ayman Musa
7c7c79c212 [X86] When applying the shuffle-to-zero-extend transformation on floating point, bitcast to integer first.
Fix issue described in PR34577.

Differential Revision: https://reviews.llvm.org/D37803

llvm-svn: 313256
2017-09-14 12:06:38 +00:00
Jonas Devlieghere
0a12d5c67d [dwarfdump] Add DWARF verifiers for address ranges
This patch started as an attempt to rebase Greg's differential (D32821).
The result is both quite similar and different at the same time. It adds
the following checks:

 - Verify that all address ranges in a DIE are valid.
 - Verify that no ranges within the DIE overlap.
 - Verify that no ranges overlap with the ranges of a sibling.
 - Verify that children are completely contained in its (direct)
   parent's address range. (unless both are subprograms)

Differential revision: https://reviews.llvm.org/D37696

llvm-svn: 313255
2017-09-14 11:33:42 +00:00
Simon Dardis
c2db7efb6c [mips] Pick the right variant of DINS upfront and enable target instruction verification
This patch complements D16810 "[mips] Make isel select the correct DEXT variant
up front.". Now ISel picks the right variant of DINS, so now there is no need
to replace DINS with the appropriate variant during
MipsMCCodeEmitter::encodeInstruction().

This patch also enables target specific instruction verification for ins, dins,
dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that
are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these
constraints are not checked during instruction selection. Adding machine
verification should catch outstanding cases.

Finally, correct a bug that instruction verification uncovered, where the
position operand of a DINSU generated during lowering was being silently
and accidently corrected to the correct value.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D34809

llvm-svn: 313254
2017-09-14 10:58:00 +00:00
Jonas Devlieghere
e1e2b6ad2d Revert "[dwarfdump] Add DWARF verifiers for address ranges"
This reverts commit r313250.

llvm-svn: 313253
2017-09-14 10:49:15 +00:00
Simon Pilgrim
a9a617e651 [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
We already have a combine for this pattern when the input to shl is add, so we just need to enable the transformation when the input is or.

Original patch by @tstellar

Differential Revision: https://reviews.llvm.org/D19325

llvm-svn: 313251
2017-09-14 10:38:30 +00:00
Jonas Devlieghere
8bc89997a1 [dwarfdump] Add DWARF verifiers for address ranges
This patch started as an attempt to rebase Greg's differential (D32821).
The result is both quite similar and different at the same time. It adds
the following checks:

 - Verify that all address ranges in a DIE are valid.
 - Verify that no ranges within the DIE overlap.
 - Verify that no ranges overlap with the ranges of a sibling.
 - Verify that children are completely contained in its (direct)
   parent's address range. (unless both are subprograms)

Differential revision: https://reviews.llvm.org/D37696

llvm-svn: 313250
2017-09-14 10:38:18 +00:00
Simon Pilgrim
d368977d6f Fix line endings. NFCI.
llvm-svn: 313247
2017-09-14 10:30:54 +00:00
Simon Pilgrim
3029ee7a59 Fix line endings. NFCI.
llvm-svn: 313246
2017-09-14 10:30:22 +00:00
Simon Pilgrim
efa82226b8 [SelectionDAG] ComputeNumSignBits - cleanup ROTL/ROTR wrapping to match DAGCombine etc.
Use RotAmt.urem(VTBits) instead of AND(RotAmt, VTBits - 1)

TBH I don't expect non-power-of-2 types to be created, but it makes the logic clearer and matches what we do in other rotation combines.

llvm-svn: 313245
2017-09-14 10:28:01 +00:00
Dean Michael Berris
d08c7b8d9c [XRay][DebugInfo] Update the test to use a specific target
Follow-up to D37791.

llvm-svn: 313243
2017-09-14 09:58:25 +00:00
Chandler Carruth
9586106cf5 [PM/CGSCC] Teach the CGSCC pass manager components to gracefully handle
invalidated SCCs even when we do not have an updated SCC to redirect
towards.

This comes up in a fairly subtle and surprising circumstance: we need to
have a connected but internal node in the call graph which later becomes
a disconnected island, and then gets deleted. All of this needs to
happen mid-CGSCC walk. Because it is disconnected, we have no way of
computing a new "current" SCC when it gets deleted. Instead, we need to
explicitly check for a deleted "current" SCC and bail out of the current
CGSCC step. This will bubble all the way up to the post-order walk and
then resume correctly.

I've included minimal tests for this bug. The specific behavior
matches something we've seen in the wild with the new PM combined with
ThinLTO and sample PGO, but I've not yet confirmed whether this is the
only issue there.

llvm-svn: 313242
2017-09-14 08:33:57 +00:00
Dean Michael Berris
91028c0135 [XRay][DebugInfo] Remove -debug-compile from test invocation of llc
This breaks bootstrap builds, and is actually unnecessary. Tested
locally and it seems we can remove -debug-comile just fine.

Follow-up to D37791.

llvm-svn: 313238
2017-09-14 07:54:54 +00:00