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Commit Graph

181321 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
97be7d7df2 [Remarks] Require an explicit format to the parser
Make the parser require an explicit format.

This allows new formats to be easily added by following YAML as an
example.

llvm-svn: 365102
2019-07-04 00:31:03 +00:00
Francis Visoiu Mistrih
386dd80250 [Remarks][NFC] Move the string table parsing out of the parser constructor
Make the parser take an already-parsed string table.

llvm-svn: 365101
2019-07-04 00:30:58 +00:00
Derek Schuff
f8c876ff3b [WebAssembly] Update test failure explanations
llvm-svn: 365100
2019-07-04 00:24:35 +00:00
Shoaib Meenai
8170d669b1 [MachO] Add valid architecture function
Added array of valid architectures and function returning array.
Modified llvm-lipo to include list of valid architectures in error message for invalid arch.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D63735

llvm-svn: 365099
2019-07-04 00:17:02 +00:00
Lang Hames
07ff51c0a6 [JITLink][ORC] Add EHFrameRegistrar interface, use in EHFrameRegistrationPlugin.
Replaces direct calls to eh-frame registration with calls to methods on an
EHFrameRegistrar instance. This allows clients to substitute a registrar that
registers frames in a remote process via IPC/RPC.

llvm-svn: 365098
2019-07-04 00:05:12 +00:00
Reid Kleckner
f7383bbaa1 Revert [ThinLTO] Optimize writeonly globals out
This reverts r365040 (git commit 5cacb914758c7f436b47c8362100f10cef14bbc4)

Speculatively reverting, since this appears to have broken check-lld on
Linux. Partial analysis in https://crbug.com/981168.

llvm-svn: 365097
2019-07-04 00:03:30 +00:00
Derek Schuff
05a21c822b [WebAssembly] Enable IndirectBrExpandPass
Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.

Fixes PR42498

Reviewers: aheejin

Differential Revision: https://reviews.llvm.org/D64161

llvm-svn: 365096
2019-07-03 23:54:06 +00:00
Matt Arsenault
26e5d021eb AMDGPU: Add pass to lower SGPR spills
This is split out from my patches to split register allocation into a
separate SGPR and VGPR phase, and has some parts that aren't yet used
(like maintaining LiveIntervals).

This simplifies making the frame pointer register callee saved. As it
is now, the code to determine callee saves needs to predict all the
possible SGPR spills and how many callee saved VGPRs are needed. By
handling this before PrologEpilogInserter, it's possible to just check
the spill objects that already exist.

Change-Id: I29e6df4034afcf949e06f8ef44206acb94696f04
llvm-svn: 365095
2019-07-03 23:32:29 +00:00
Eli Friedman
ac9dc6f8fc [JumpThreading] Fix threading with unusual PHI nodes.
If the block being cloned contains a PHI node, in general, we need to
clone that PHI node, even though it's trivial. If the operand of the PHI
is an instruction in the block being cloned, the correct value for the
operand doesn't exist until SSAUpdater constructs it.

We usually don't hit this issue because we try to avoid threading across
loop headers, but it's possible to hit this in some cases involving
irreducible CFGs.  I added a flag to allow threading across loop headers
to make the testcase easier to understand.

Thanks to Brian Rzycki for reducing the testcase.

Fixes https://bugs.llvm.org/show_bug.cgi?id=42085.

Differential Revision: https://reviews.llvm.org/D63913

llvm-svn: 365094
2019-07-03 23:12:39 +00:00
Matt Arsenault
1b188a9118 GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUES
llvm-svn: 365093
2019-07-03 23:08:06 +00:00
Francis Visoiu Mistrih
972459e6ed [Bitcode] Move Bitstream to a separate library
This moves Bitcode/Bitstream*, Bitcode/BitCodes.h to Bitstream/.

This is needed to avoid a circular dependency when using the bitstream
code for parsing optimization remarks.

Since Bitcode uses Core for the IR part:

libLLVMRemarks -> Bitcode -> Core

and Core uses libLLVMRemarks to generate remarks (see
IR/RemarkStreamer.cpp):

Core -> libLLVMRemarks

we need to separate the Bitstream and Bitcode part.

For clang-doc, it seems that it doesn't need the whole bitcode layer, so
I updated the CMake to only use the bitstream part.

Differential Revision: https://reviews.llvm.org/D63899

llvm-svn: 365091
2019-07-03 22:40:07 +00:00
Guanzhong Chen
94ed17a41b [WebAssembly][NFC] simplify SjLj inline assembly test
Summary:
Per feedback in D64115, simplify the test.

`hidden` is left in though, because every test in the file has it.

Reviewers: aheejin, tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64117

llvm-svn: 365089
2019-07-03 22:11:14 +00:00
Thomas Lively
3ab55228e0 [WebAssembly] Add option to emit passive segments
Summary:
Adds `--passive-segments` and `--active-segments` flags to control
what kind of segments are emitted. For now the default is always
to emit active segments so this is not a breaking change, but in
the future the default will be changed to passive segments when
shared memory is requested and active segments otherwise. When
passive segments are emitted, corresponding memory.init and
data.drop instructions are emitted in a `__wasm_init_memory`
function that is automatically called at the beginning of
`__wasm_call_ctors`.

Reviewers: sbc100, aheejin, dschuff

Subscribers: azakai, dschuff, jgravelle-google, sunfish, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59343

llvm-svn: 365088
2019-07-03 22:04:54 +00:00
Matt Arsenault
78d62ad72d Revert "[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type."
This reverts commit r365073.

This is crashing, and is improperly relying on IR type names.

llvm-svn: 365087
2019-07-03 21:34:34 +00:00
JF Bastien
be75ae7b0e Revert "[llvm-ar][test] Add to MRI test coverage"
This reverts commit 250015bacf7f255abcfb646fb8b6b56ce8be7e01.
r365039 was re-commit of D63197 and failed on Mac. Reid XFAIL'd it, but I'd rather jsut revert and have it fixed properly.

llvm-svn: 365084
2019-07-03 20:47:53 +00:00
Evgeniy Stepanov
c263f5e880 Teach ValueTracking that aarch64.irg result aliases its input.
Reviewers: javed.absar, olista01

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64103

llvm-svn: 365079
2019-07-03 20:19:14 +00:00
Florian Hahn
0394dff601 [LoopBase] Strengthen isLoopExiting by requiring that BB must be inside the loop.
Currently isLoopExiting returns true for BBs that are not part of the
loop. To avoid hiding subtle bugs, this patch adds an assertion to make
sure the passed BB is inside the loop

Reviewers: reames, efriedma, hfinkel, arsenm, nhaehnle

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D63952

llvm-svn: 365077
2019-07-03 20:15:14 +00:00
Reid Kleckner
710094af7f Try to XFAIL mri-utf8.test on Mac
llvm-svn: 365076
2019-07-03 20:14:54 +00:00
Philip Reames
45f8df4a39 [LFTR] Use SCEVExpander for the pointer limit case instead of manual IR gen
As noted in the test change, this is not trivially NFC, but all of the changes in output are cases where the SCEVExpander form is more canonical/optimal than the hand generation.  

llvm-svn: 365075
2019-07-03 20:03:46 +00:00
Konstantin Pyzhov
df53ea7203 [AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.
Summary:
Hip texture type is equivalent to OpenCL image. So, we need to set the Image type for kernel arguments with __hip_texture type.

Differential revision: https://reviews.llvm.org/D63850

llvm-svn: 365073
2019-07-03 19:11:35 +00:00
Philip Reames
1d97c340ea [LFTR] Remove a stray variable shadow *of the same value* [NFC]
llvm-svn: 365072
2019-07-03 19:08:43 +00:00
Philip Reames
e44b7785ef [LFTR] Style and comment changes to clarify the narrow vs wide bitwidth evaluation behavior [NFC]
llvm-svn: 365071
2019-07-03 19:03:37 +00:00
Philip Reames
b00d273c24 [LFTR] Sink the decision not use truncate scheme for constants into genLoopLimit [NFC]
We might as well just evaluate the constants using SCEV, and having the cases grouped makes the logic slightly easier to read anyway.

llvm-svn: 365070
2019-07-03 18:41:03 +00:00
Jessica Paquette
1ad3046b4f Fix precedence in assert from r364961
Precedence was wrong in an assert added in r364961. Add braces around the
assertion condition to make it right.

See: https://reviews.llvm.org/D64084
llvm-svn: 365069
2019-07-03 18:30:01 +00:00
Philip Reames
516a32fa5d [LFTR] Remove falsely generalized (dead) code [NFC]
llvm-svn: 365067
2019-07-03 18:24:06 +00:00
Philip Reames
22a6f8f27d [LFTR] Hoist extend expressions outside of loops w/o waiting for LICM
The motivation for this is two fold:
1) Make the output (and thus tests)  a bit more readable to a human trying to understand the result of the transform
2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default)

llvm-svn: 365066
2019-07-03 18:18:36 +00:00
Alex Lorenz
da15aa4d0d [macCatalyst] Print out macCatalyst in llvm-objdump for the platform
'macCatalyst' is more readable than 'maccatalyst'.

llvm-svn: 365064
2019-07-03 17:46:30 +00:00
Jessica Paquette
31937cf55f [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed
Instead of just stopping to see if we have a G_CONSTANT, instead, look through
G_TRUNCs, G_SEXTs, and G_ZEXTs.

This gives an average ~1.3% code size improvement on CINT2000 at -O3.

Differential Revision: https://reviews.llvm.org/D64108

llvm-svn: 365063
2019-07-03 17:46:23 +00:00
Robert Lougher
567aeabb96 [X86] Update test; NFC
This updates pr38743.ll after D62605.

llvm-svn: 365062
2019-07-03 17:45:24 +00:00
Robert Lougher
bc8c35fe89 [X86] Avoid SFB - Skip meta instructions
This patch generalizes the fix in D61680 to ignore all meta instructions,
not just debug info.

Patch by Chris Dawson.

Differential Revision: https://reviews.llvm.org/D62605

llvm-svn: 365061
2019-07-03 17:43:55 +00:00
Joel E. Denny
44dc561730 [Bitcode] Update CHECK-DAG usage in tests
This patch adjusts tests not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of
`CHECK-DAG` directives:

1. `thinlto-function-summary-originalnames.ll`: The directive with the
pattern `<COMBINED` is surely intended to match `<COMBINED ` (note the
trailing space), but it instead matches
`<COMBINED_GLOBALVAR_INIT_REFS`, for which there is a separate
directive.  With the deprecated behavior, both directives match the
latter text and neither match the former text.  I've adjusted the
former directive so it matches only the former text.

2. `thinlto-summary-local-5.0.ll`: Two directives have identical
patterns when they were clearly meant to have different patterns.

3. `upgrade-pointer-address-space.ll`: There are three identical
directives but only two occurrences of the matching text.  With the
deprecated behavior, they always match exactly the same text, so the
behavior can't have been useful.  I removed one of the directives and
converted the other two from `CHECK-DAG` to `CHECK`.

Reviewed By: probinson, aprantl

Differential Revision: https://reviews.llvm.org/D64036

llvm-svn: 365060
2019-07-03 17:31:43 +00:00
Francis Visoiu Mistrih
f0c4b59ebb [CodeGen] Make branch funnels pass the machine verifier
We previously marked all the tests with branch funnels as
`-verify-machineinstrs=0`.

This is an attempt to fix it.

1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList =
(outs)`

2) After that we hit an assert: ``` Assertion failed: (Op.getValueType()
!= MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue
operands should occur at end of operand list!"), function AddOperand,
file
/Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp,
line 461.  ```

The chain operand was added at the beginning of the operand list. Move
that to the end.

3) After that we hit another verifier issue in the pseudo expansion
where the registers used in the cmps and jmps are not added to the
livein lists. Add the `EFLAGS` to all the new MBBs that we create.

PR39436

Differential Review: https://reviews.llvm.org/D54155

llvm-svn: 365058
2019-07-03 17:16:45 +00:00
Simon Pilgrim
22b3aa27a6 [X86] ComputeNumSignBitsForTargetNode - add target shuffle support.
llvm-svn: 365057
2019-07-03 17:06:59 +00:00
Roman Lebedev
df3ce19537 [NFC][InstCombine] onehot_merge.ll: add last few tests in the state they regress to in D62818
llvm-svn: 365056
2019-07-03 16:48:53 +00:00
Sanjay Patel
c04ead4c31 [SLP] add tests for bitcasted vector pointer load; NFC
I'm not sure if this falls within the scope of SLP,
but we could create vector loads for some of these
patterns.

llvm-svn: 365055
2019-07-03 16:46:14 +00:00
Amaury Sechet
43ae03fef5 Use getAllOnesConstants instead of -1 in DAGCombiner. NFC
llvm-svn: 365054
2019-07-03 16:34:36 +00:00
Philip Reames
2d847caee5 [SCEV] Preserve flags on add/muls in getSCEVATScope
We haven't changed the set of users, just specialized an operand for those users.  Given that, the previous wrap flags must still be correct.

Sorry for the lack of test case.  Noticed this while working on something else, and haven't figured out to exercise this standalone.

llvm-svn: 365053
2019-07-03 16:34:08 +00:00
Amaury Sechet
ece7389166 [DAGCombine] More diamong carry pattern optimization.
Summary:
This diff improve the capability of DAGCOmbine to generate linear carries propagation in presence of a diamond pattern. It is now able to match a large variety of different patterns rather than some hardcoded one.

Arguably, the codegen in test cases is not better, but this is to be expected. The goal of this transformation is more about canonicalisation than actual optimisation.

Reviewers: hfinkel, RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57302

llvm-svn: 365051
2019-07-03 16:15:59 +00:00
Simon Pilgrim
c473b8b6bd [X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
If we have more then 2 shuffle ops to combine, try to use combineX86ShuffleChainWithExtract to see if some are from the same super vector.

llvm-svn: 365050
2019-07-03 15:46:08 +00:00
Teresa Johnson
755dc0300b [ThinLTO] Fix gcc warnings from commit
Remove an unnecessary const from an Optional return type introduced
in r364960 that gcc 7.4.0 warns about. It is unnecessary and possibly
incorrect.

llvm-svn: 365047
2019-07-03 15:12:38 +00:00
Sam Parker
98e899e1ff [ARM] Fix for NDEBUG builds
Fix unused variable warning as well as a nonsense assert.

Differential Revision: https://reviews.llvm.org/D63816

llvm-svn: 365046
2019-07-03 14:39:23 +00:00
Simon Pilgrim
c1766168d9 [X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))
iff the number of elements doesn't change.

This gets around an issue with combineX86ShuffleChain not being able to hint which domain is preferred for shuffles that can be done with either.

Fixes regression introduced in rL365041

llvm-svn: 365044
2019-07-03 14:34:16 +00:00
James Molloy
8f41221e00 [SelectionDAG] Propagate alias metadata to target intrinsic nodes
When a target intrinsic has been determined to touch memory, we construct a MachineMemOperand during SDAG construction. In this case, we should propagate AAMDNodes metadata to the MachineMemOperand where available.

Differential revision: https://reviews.llvm.org/D64131

llvm-svn: 365043
2019-07-03 14:33:29 +00:00
James Henderson
56fa2402b4 [docs][llvm-objcopy] Write documentation for llvm-objcopy
This patch addresses https://bugs.llvm.org/show_bug.cgi?id=42183 by replacing
the stub markdown doc for llvm-objcopy with a full one describing the current
options available in llvm-objcopy.

Reviewed by: jakehehrlich, MaskRay

Differential Revision: https://reviews.llvm.org/D63820

llvm-svn: 365042
2019-07-03 14:21:48 +00:00
Simon Pilgrim
aecf76eaad [X86][AVX] combineX86ShuffleChainWithExtract - add number of non-zero extract_subvectors to the combine depth
This better accounts for the cost/benefit of removing extract_subvectors from the shuffle and will be more useful in future patches.

The vpermq predicate regression will be fixed shortly.

llvm-svn: 365041
2019-07-03 14:17:21 +00:00
Eugene Leviant
a4bd29ba06 [ThinLTO] Optimize writeonly globals out
Differential revision: https://reviews.llvm.org/D63444

llvm-svn: 365040
2019-07-03 14:14:52 +00:00
Owen Reynolds
b1b8c2c4a3 [llvm-ar][test] Add to MRI test coverage
This reapplies 363232 that was reverted due to a buildbot test failure, this build bot has now been fixed.

Differential Revision: https://reviews.llvm.org/D63197

llvm-svn: 365039
2019-07-03 13:47:29 +00:00
Simon Atanasyan
303ac16b7c [mips] Mark general scheduling model as complete
llvm-svn: 365034
2019-07-03 12:28:05 +00:00
Simon Atanasyan
3e3ce7afa8 [mips] Add missing atomic instructions to general scheduling definitions
llvm-svn: 365033
2019-07-03 12:27:58 +00:00
Simon Atanasyan
9c7be48c15 [mips] Add missing microMIPS instructions to general scheduling definitions
llvm-svn: 365032
2019-07-03 12:27:51 +00:00