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Author SHA1 Message Date
Jakob Stoklund Olesen
d0c1eb9dd2 Don't adjust for alignment padding in OffsetIsInRange. 
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

llvm-svn: 146751
 2011-12-16 19:10:00 +00:00
Benjamin Kramer
04d6a4c456 Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

llvm-svn: 146750
 2011-12-16 19:08:59 +00:00
Devang Patel
1b525a0c23 In DICompositeType, referenced to derived type is either metadata or null. 
llvm-svn: 146744
 2011-12-16 17:51:31 +00:00
Devang Patel
59f6d6e2d1 Clarify and fix subprogram description. 
llvm-svn: 146743
 2011-12-16 17:50:04 +00:00
Jakob Stoklund Olesen
3d0382e29d Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739
 2011-12-16 16:07:41 +00:00
Manuel Klimek
2f7cf4e64b Adds a JSON parser and a benchmark (json-bench) to catch performance regressions. 
llvm-svn: 146735
 2011-12-16 13:09:10 +00:00
Chandler Carruth
9ad7094a8c Put the '*' in the right place in the unit test. Forgot to fix up this 
bit of style, sorry.

llvm-svn: 146733
 2011-12-16 09:37:55 +00:00
Chandler Carruth
0339ff36c1 Make GCC happy by using makeAraryRef instead of the implicit conversion. 
I have no idea why GCC can't cope with the implicit conversion and Clang
can, or whose bug it is. Grr.

llvm-svn: 146732
 2011-12-16 09:36:16 +00:00
Chandler Carruth
1cf4d2d1ae Add a generic collection of class templates to ADT for building 
variadic-like functions in C++98. See the comments in the header file
for a more detailed description of how these work. We plan to use these
extensively in the AST matching library. This code and idea were
originally authored by Zhanyong Wan. I've condensed it using macros
to reduce repeatition and adjusted it to fit better with LLVM's ADT.

Thanks to both David Blaikie and Doug Gregor for the review!

llvm-svn: 146729
 2011-12-16 08:58:59 +00:00
Chris Lattner
26f06c927f By popular demand, link up types by name if they are isomorphic and one is an 
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.

llvm-svn: 146728
 2011-12-16 08:36:07 +00:00
Craig Topper
88e2bfef0a Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
llvm-svn: 146726
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
e7a3e38c9e Tweak CMake build on Cygwin. 
llvm-svn: 146725
 2011-12-16 06:21:08 +00:00
NAKAMURA Takumi
1aaed909ae Target/Hexagon: Fix CMake build. 
llvm-svn: 146724
 2011-12-16 06:21:02 +00:00
Andrew Trick
df958760c8 Avoid a confusing assert for silly options: -unroll-runtime -unroll-count=1. 
No need for an explicit test case for an unsupported combination of options.

llvm-svn: 146721
 2011-12-16 02:03:48 +00:00
Kostya Serebryany
c78b00cab4 [asan] add a test for instrumenting globals 
llvm-svn: 146718
 2011-12-16 01:28:19 +00:00
Jim Grosbach
42bf8d8526 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jakob Stoklund Olesen
f51f7724cb Extract a method. No functional change. 
llvm-svn: 146713
 2011-12-16 00:12:05 +00:00
Daniel Dunbar
68de82c003 llvm-config: Fix --targets-built, I changed this to use the registry but wasn't 
properly initializing the target infos. I decided it wasn't worth linking them
in for this, so just switched back to using the Makefile variable for now. We
can reconsider later if we ever get pluggable targets.

llvm-svn: 146711
 2011-12-16 00:04:43 +00:00
Jim Grosbach
5f14a4c5d4 Thumb2 ADR assembly parsing w/o the .w suffix. 
llvm-svn: 146710
 2011-12-15 23:52:17 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Daniel Dunbar
f961e224ec llvm-config: Update help text for removal of "backend" pseudo component. 
llvm-svn: 146708
 2011-12-15 23:43:17 +00:00
Daniel Dunbar
d2627d2855 build/unittests: Fix llvm-config names for gtest libraries, and bring Makefile 
library names in line with those used by CMake.
 - Patch by Johannes Obermayr, with tweaks by me.

llvm-svn: 146706
 2011-12-15 23:35:08 +00:00
Nick Lewycky
88e64bacfa Move parts of lib/Target that use CodeGen into lib/CodeGen. 
llvm-svn: 146702
 2011-12-15 22:58:58 +00:00
Eli Friedman
7e3cbd0db2 Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
llvm-svn: 146700
 2011-12-15 22:56:53 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Kostya Serebryany
847d2d2c25 [asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports. 
llvm-svn: 146698
 2011-12-15 22:55:55 +00:00
Tony Linthicum
31c6f9b096 Add MCTargetDesc library to Hexagon target 
llvm-svn: 146692
 2011-12-15 22:29:08 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
cd03c93e33 Enable proper constant island alignment by default. 
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690
 2011-12-15 22:14:45 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Kostya Serebryany
65849ee22a [asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part. 
llvm-svn: 146688
 2011-12-15 21:59:03 +00:00
Jim Grosbach
3ee3c6dc3e Silence warning. 
llvm-svn: 146686
 2011-12-15 21:54:55 +00:00
Jim Grosbach
8ed1253ef3 ARM NEON two-register double spaced register list parsing support. 
llvm-svn: 146685
 2011-12-15 21:44:33 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Eli Friedman
8a99f9655e Zap unnecessary semicolons. 
llvm-svn: 146682
 2011-12-15 21:11:38 +00:00
Lang Hames
d5cee672a7 Set specific target cpu for testcase. 
llvm-svn: 146678
 2011-12-15 20:22:34 +00:00
Lang Hames
0e361e816d Added test case for r146671. 
llvm-svn: 146675
 2011-12-15 19:56:07 +00:00
Jakob Stoklund Olesen
bc821819f3 Use the proper comparator for set_intersection. 
llvm-svn: 146674
 2011-12-15 19:26:23 +00:00
Lang Hames
d86b47a279 Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>. 
llvm-svn: 146671
 2011-12-15 18:57:27 +00:00
Devang Patel
b8b77459d6 Update DebugLoc while merging nodes at -O0. 
Patch by Kyriakos Georgiou!

llvm-svn: 146670
 2011-12-15 18:21:18 +00:00
Hal Finkel
e8220d9927 Add a test case to make sure that the nop really does follow the bl on ppc64 elf 
llvm-svn: 146666
 2011-12-15 17:59:23 +00:00
Devang Patel
9578694f5b Virtual table holder field is either metadata or null. 
llvm-svn: 146665
 2011-12-15 17:55:56 +00:00
Hal Finkel
f480143f08 Ensure that the nop that should follow a bl call in PPC64 ELF actually does 
llvm-svn: 146664
 2011-12-15 17:54:01 +00:00
Jakob Stoklund Olesen
9945c85b52 Synthesize missing register class intersections. 
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

llvm-svn: 146657
 2011-12-15 16:48:55 +00:00
Richard Osborne
5f2d0e64e0 Pass optLevel to XCoreDAGToDAGISel. 
Patch by Kyriakos Georgiou.

llvm-svn: 146656
 2011-12-15 15:18:35 +00:00
Eli Friedman
09abc453ac Fix test. 
llvm-svn: 146642
 2011-12-15 04:52:47 +00:00
Eli Friedman
f6ae3a7caf Make constant folding for GEPs a bit more aggressive. 
llvm-svn: 146639
 2011-12-15 04:33:48 +00:00
Eli Friedman
71c0914b64 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. 
llvm-svn: 146630
 2011-12-15 02:07:20 +00:00
Chad Rosier
dcfc5e1dd0 Use SmallVector/assign(), rather than std::vector/push_back(). 
llvm-svn: 146627
 2011-12-15 01:16:09 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00