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79 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
46bdb4d45e [Hexagon] Remove 'T' from HasVNN predicates, NFC 
Patch by Sumanth Gundapaneni.

llvm-svn: 335124
 2018-06-20 13:56:09 +00:00
Krzysztof Parzyszek
90f9f3ddd4 [DAGCombiner] Recognize more patterns for ABS 
Differential Revision: https://reviews.llvm.org/D47831

llvm-svn: 334553
 2018-06-12 21:51:49 +00:00
Krzysztof Parzyszek
cca7086924 [SelectionDAG] Provide default expansion for rotates 
Implement default legalization of rotates: either in terms of the rotation
in the opposite direction (if legal), or in terms of shifts and ors.

Implement generating of rotate instructions for Hexagon. Hexagon only
supports rotates by an immediate value, so implement custom lowering of
ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion.

Differential Revision: https://reviews.llvm.org/D47725

llvm-svn: 334497
 2018-06-12 12:49:36 +00:00
Krzysztof Parzyszek
6c9d726977 [Hexagon] Add pattern to generate 64-bit neg instruction 
llvm-svn: 334043
 2018-06-05 19:52:39 +00:00
Krzysztof Parzyszek
4a42c82327 [Hexagon] Add more patterns for generating abs/absp instructions 
llvm-svn: 334038
 2018-06-05 19:00:50 +00:00
Krzysztof Parzyszek
309f570ea8 [Hexagon] Add patterns for accumulating HVX compares 
llvm-svn: 333009
 2018-05-22 18:27:02 +00:00
Krzysztof Parzyszek
a4467d89bc [Hexagon] Add a target feature for memop generation 
llvm-svn: 332285
 2018-05-14 20:09:07 +00:00
Krzysztof Parzyszek
fbff7667ba [Hexagon] Avoid predicate copies to integer registers from store-locked 
llvm-svn: 332260
 2018-05-14 16:41:40 +00:00
Krzysztof Parzyszek
d11cd46c0c [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops 
llvm-svn: 330330
 2018-04-19 14:24:31 +00:00
Krzysztof Parzyszek
071a8678db [Hexagon] Fix zero-extending non-HVX bool vectors 
llvm-svn: 327712
 2018-03-16 15:03:37 +00:00
Krzysztof Parzyszek
71647c0d9d [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones 
This is a follow-up to r325169, this time for all types, not just HVX
vector types.

Disable this by default, since it's not always safe. 

llvm-svn: 326915
 2018-03-07 17:27:18 +00:00
Krzysztof Parzyszek
32fce8da35 [Hexagon] Add patterns for compares of i1 values 
llvm-svn: 326220
 2018-02-27 18:31:46 +00:00
Amaury Sechet
b89f706ba3 [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner. 
Summary:
There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs.

Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond.

Reviewers: spatel, hfinkel, niravd, craig.topper

Subscribers: nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D41235

llvm-svn: 325892
 2018-02-23 11:50:42 +00:00
Krzysztof Parzyszek
d760dbf10e [Hexagon] Split HVX vector pair loads/stores, expand unaligned loads 
llvm-svn: 325169
 2018-02-14 20:46:06 +00:00
Krzysztof Parzyszek
f51472dbd6 [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC 
llvm-svn: 324392
 2018-02-06 20:22:20 +00:00
Krzysztof Parzyszek
e747b538c8 [Hexagon] Split HVX operations on vector pairs 
Vector pairs are legal types, but not every operation can work on pairs.
For those operations that are legal for single vectors, generate a concat
of their results on pair halves.

llvm-svn: 324350
 2018-02-06 14:24:57 +00:00
Krzysztof Parzyszek
0c375edf16 [Hexagon] Handle lowering of SETCC via setCondCodeAction 
It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.

llvm-svn: 324348
 2018-02-06 14:16:52 +00:00
Krzysztof Parzyszek
b2def67068 [Hexagon] Implement HVX codegen for vector shifts 
llvm-svn: 323914
 2018-01-31 20:49:24 +00:00
Krzysztof Parzyszek
fcb6fc5908 [Hexagon] Generate constant splats instead of loads from constant pool 
llvm-svn: 323568
 2018-01-26 21:54:56 +00:00
Krzysztof Parzyszek
4391d3c641 [Hexagon] Remove unused HexagonISD opcodes, NFC 
llvm-svn: 323324
 2018-01-24 14:07:37 +00:00
Krzysztof Parzyszek
43f3c72b7f [Hexagon] Add patterns for sext_inreg of HVX vector types 
llvm-svn: 323250
 2018-01-23 19:56:16 +00:00
Krzysztof Parzyszek
c2af269623 [Hexagon] Implement basic vector operations on vectors vNi1 
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.

llvm-svn: 323229
 2018-01-23 17:53:59 +00:00
Krzysztof Parzyszek
5e1e967ddf [Hexagon] Implement signed and unsigned multiply-high for vectors 
llvm-svn: 322499
 2018-01-15 18:43:55 +00:00
Krzysztof Parzyszek
0006e274c7 [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors 
Recommit r321897 with updated testcases.

llvm-svn: 321908
 2018-01-05 22:31:11 +00:00
Krzysztof Parzyszek
7e84865cb2 Revert r321894: it requires a part of another commit that is not ready yet 
Commit message:
[Hexagon] Add patterns for sext_inreg of HVX vector types

llvm-svn: 321904
 2018-01-05 21:57:43 +00:00
Krzysztof Parzyszek
ee82b27b5c Revert r321897: affected testcases were not updated 
Commit message:
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors

llvm-svn: 321902
 2018-01-05 21:50:15 +00:00
Krzysztof Parzyszek
414301cb45 [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors 
llvm-svn: 321897
 2018-01-05 20:49:26 +00:00
Krzysztof Parzyszek
8733275343 [Hexagon] Add patterns for truncating HVX vector types 
Only non-bool vectors.

llvm-svn: 321895
 2018-01-05 20:48:03 +00:00
Krzysztof Parzyszek
f32324b43f [Hexagon] Add patterns for sext_inreg of HVX vector types 
llvm-svn: 321894
 2018-01-05 20:46:41 +00:00
Krzysztof Parzyszek
f8243675c2 [Hexagon] Add pattern for vsplat to v8i8 
llvm-svn: 321892
 2018-01-05 20:43:56 +00:00
Krzysztof Parzyszek
2216e5b7a7 [Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISD 
llvm-svn: 321798
 2018-01-04 13:56:04 +00:00
Krzysztof Parzyszek
52d2737ea5 [Hexagon] Fix generation of vector sign extensions 
llvm-svn: 321650
 2018-01-02 15:28:49 +00:00
Krzysztof Parzyszek
b90ded8ab6 [Hexagon] Allow construction of HVX vector predicates 
Handle BUILD_VECTOR of boolean values.

llvm-svn: 321220
 2017-12-20 20:49:43 +00:00
Krzysztof Parzyszek
cfecd633ca [Hexagon] Generate HVX code for vector sign-, zero- and any-extends 
Implement any-extend as zero-extend.

llvm-svn: 321004
 2017-12-18 18:32:27 +00:00
Krzysztof Parzyszek
3942dc3e0b [Hexagon] Handle concat_vectors of all allowed HVX types 
llvm-svn: 320865
 2017-12-15 21:23:12 +00:00
Krzysztof Parzyszek
0c8998d812 [Hexagon] Fix operand-swapping PatFrag for atomic stores 
PatFrag now has the atomicity information stored as bit fields. They
need to be copied to the new PatFrag.

llvm-svn: 320855
 2017-12-15 20:13:57 +00:00
Krzysztof Parzyszek
1eb78fb8be [Hexagon] Generate HVX code for comparisons and selects 
llvm-svn: 320744
 2017-12-14 21:28:48 +00:00
Krzysztof Parzyszek
f4e269a95c [Hexagon] Remove vectors of i64 from valid HVX types 
HVX does not support operations on 64-bit integers.

llvm-svn: 320722
 2017-12-14 18:35:24 +00:00
Krzysztof Parzyszek
3bf791b091 [Hexagon] Generate HVX code for basic arithmetic operations 
Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.

llvm-svn: 320063
 2017-12-07 17:37:28 +00:00
Krzysztof Parzyszek
eec0895eab [Hexagon] Generate HVX code for vector construction and access 
Support for:
  - build vector,
  - extract vector element, subvector,
  - insert vector element, subvector,
  - shuffle.

llvm-svn: 319901
 2017-12-06 16:40:37 +00:00
Krzysztof Parzyszek
ac90d004e1 [Hexagon] Remove HexagonISD::PACKHL 
llvm-svn: 319352
 2017-11-29 19:59:29 +00:00
Krzysztof Parzyszek
2a2b3cd66d [Hexagon] Add patterns to select A2_combine_ll and its variants 
llvm-svn: 318876
 2017-11-22 20:55:41 +00:00
Krzysztof Parzyszek
e437332dc6 [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr 
If the offset is an immediate, avoid putting it in a register
to get Rs+Rt<<#0.

llvm-svn: 317275
 2017-11-02 21:56:59 +00:00
Krzysztof Parzyszek
a326e2735d [Hexagon] Adjust patterns to reflect instruction selection preferences 
llvm-svn: 316804
 2017-10-27 22:24:49 +00:00
Krzysztof Parzyszek
d67f165bc2 [Hexagon] Add extra pattern for S4_addaddi 
One combination was missing: add(add(x,y),c).

llvm-svn: 316363
 2017-10-23 19:07:50 +00:00
Krzysztof Parzyszek
8d03b9529a [Hexagon] Reorganize and update instruction patterns 
llvm-svn: 316228
 2017-10-20 19:33:12 +00:00
Krzysztof Parzyszek
b3ac829dc5 [Hexagon] Add patterns for cmpb/cmph with immediate arguments 
Patch by Sumanth Gundapaneni.

llvm-svn: 315692
 2017-10-13 15:43:12 +00:00
Krzysztof Parzyszek
325bb38667 [Hexagon] Switch to parameterized register classes for HVX 
This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).

llvm-svn: 313362
 2017-09-15 15:46:05 +00:00
Krzysztof Parzyszek
afff3fc916 [Hexagon] Remove custom lowering of loads of v4i16 
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.

llvm-svn: 308186
 2017-07-17 15:45:45 +00:00
Krzysztof Parzyszek
f2f4bc1138 [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFC 
This breaks up pack-even and pack-odd into two separate operations.

llvm-svn: 308049
 2017-07-14 19:02:32 +00:00