Chris Lattner
06282f51cf
Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile
...
interface.
llvm-svn: 22282
2005-06-25 02:48:37 +00:00
Andrew Lenharth
4fd2bde906
If we support structs as va_list, we must pass pointers to them to va_copy
...
See last commit for LangRef, this implements it on all targets.
llvm-svn: 22273
2005-06-22 21:04:42 +00:00
Andrew Lenharth
a9214fec08
core changes for varargs
...
llvm-svn: 22254
2005-06-18 18:34:52 +00:00
Reid Spencer
678c9a3b00
Clean up some uninitialized variables and missing return statements that
...
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.
llvm-svn: 22249
2005-06-18 17:37:34 +00:00
Chris Lattner
70914ca850
silence incredibly braindead GCC 4 warning
...
llvm-svn: 22246
2005-06-17 13:44:07 +00:00
Nate Begeman
12cd2d8d99
Commit fix for generating conditional branch pseudo instructions that
...
avoids dereferencing the end() iterator when selecting the fallthrough
block. This requires an ilist change.
llvm-svn: 22212
2005-06-15 18:22:43 +00:00
Nate Begeman
9bb1be2eec
Commit a small improvement that is already in the x86 and ia64 backends to
...
not generate unnecessary register copies. This improves compile time by
2-5% depending on the test.
llvm-svn: 22210
2005-06-14 03:55:23 +00:00
Nate Begeman
f516b866e5
Fix a memory smasher caught by Mac OS X's debug malloc library. We were
...
incorrectly using an iterator after it was invalid.
llvm-svn: 22207
2005-06-12 23:50:33 +00:00
Reid Spencer
a88b91d681
For PR572:
...
Undefine the PPC symbol which is defined by Linux/PPC (erroneously) so it
doesn't pollute the user namespace and clash with our namespace declarations.
llvm-svn: 22202
2005-06-08 17:44:48 +00:00
Nate Begeman
47cd13d42a
Handle some more real world cases of rlwimi. These don't come up that
...
regularly in "normal" code, but for things like software graphics, they
make a big difference.
For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
unsigned tmpA,tmpB,mixed;
tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}
We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
andi. r2, r4, 31775
rlwimi r2, r4, 15, 7, 11
subfic r4, r5, 32
mullw r2, r2, r4
andi. r4, r3, 31775
rlwimi r4, r3, 15, 7, 11
mullw r3, r4, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
rlwimi r3, r2, 12, 22, 26
blr
Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
slwi r2, r4, 15
rlwinm r2, r2, 0, 7, 11
andi. r4, r4, 31775
or r2, r2, r4
subfic r4, r5, 32
mullw r2, r2, r4
slwi r4, r3, 15
rlwinm r4, r4, 0, 7, 11
andi. r3, r3, 31775
or r3, r4, r3
mullw r3, r3, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
srwi r2, r2, 20
rlwimi r3, r2, 0, 22, 26
blr
llvm-svn: 22201
2005-06-08 04:14:27 +00:00
Chris Lattner
0366a913ad
PPC "branch and link" instructions are branches in the PPC sense, but not
...
in the LLVM code generator sense (they are calls). Don't mark them as such,
which fixes the regressions on the ppc tester last night
llvm-svn: 22065
2005-05-15 20:11:44 +00:00
Chris Lattner
9fc81f1162
Fix andrews changes to fit in 80 columns
...
llvm-svn: 22064
2005-05-15 19:54:37 +00:00
Chris Lattner
93007dda7d
treat TAILCALL nodes identically to CALL nodes
...
llvm-svn: 21977
2005-05-13 20:29:26 +00:00
Chris Lattner
9d788e93a6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
Chris Lattner
f8795289ff
Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll
...
llvm-svn: 21939
2005-05-13 16:20:22 +00:00
Chris Lattner
094bbfcebb
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
...
llvm-svn: 21915
2005-05-12 23:24:06 +00:00
Chris Lattner
7e08dd591c
Pass in Calling Convention to use into LowerCallTo
...
llvm-svn: 21899
2005-05-12 19:56:45 +00:00
Chris Lattner
6b0a45e42c
These targets don't like setcc
...
llvm-svn: 21884
2005-05-12 02:06:00 +00:00
Nate Begeman
e84f776b5d
Necessary changes to codegen cttz efficiently on PowerPC
...
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
llvm-svn: 21880
2005-05-11 23:43:56 +00:00
Chris Lattner
333ae3d837
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
...
include and (srl) and the inverses (shl and) etc.
llvm-svn: 21820
2005-05-09 17:39:48 +00:00
Andrew Lenharth
8e2beec4d1
fix typo
...
llvm-svn: 21693
2005-05-04 19:25:37 +00:00
Andrew Lenharth
8b64bd0fd5
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
...
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
llvm-svn: 21676
2005-05-03 17:19:30 +00:00
Chris Lattner
b0af0dd919
Doesn't support these nodes
...
llvm-svn: 21634
2005-04-30 04:26:56 +00:00
Chris Lattner
ce0d8c2408
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
...
llvm-svn: 21633
2005-04-30 04:26:06 +00:00
Andrew Lenharth
2a00530fa7
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
...
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
Misha Brukman
66d3c6e020
Convert tabs to spaces
...
llvm-svn: 21452
2005-04-22 17:54:37 +00:00
Misha Brukman
1fef885677
Remove trailing whitespace
...
llvm-svn: 21425
2005-04-21 23:30:14 +00:00
Chris Lattner
208da25af0
Match another form of eqv
...
llvm-svn: 21413
2005-04-21 21:09:11 +00:00
Chris Lattner
3d4612c54c
Add completely untested support for mtcrf/mfcrf encoding
...
llvm-svn: 21353
2005-04-19 05:41:52 +00:00
Chris Lattner
e6f861f92c
switch over the rest of the formats that use RC to use isDOT
...
llvm-svn: 21352
2005-04-19 05:21:30 +00:00
Chris Lattner
082ca8fcab
Convert the XForm instrs and XSForm instruction over to use isDOT
...
llvm-svn: 21351
2005-04-19 05:15:18 +00:00
Chris Lattner
3fdfd4e009
Now that the ppc64 and vmx operands of I are always 0, forward substitute
...
them away.
llvm-svn: 21350
2005-04-19 05:05:22 +00:00
Chris Lattner
e6f7713f03
convert over bform and iform instructions
...
llvm-svn: 21349
2005-04-19 05:00:59 +00:00
Chris Lattner
3ae0832381
Convert over DForm and DSForm instructions
...
llvm-svn: 21348
2005-04-19 04:59:28 +00:00
Chris Lattner
4ecf523af4
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
llvm-svn: 21347
2005-04-19 04:51:30 +00:00
Chris Lattner
6a2abe8591
Convert XO XS and XFX forms to use isPPC64
...
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
Chris Lattner
3cfa7a24cb
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
llvm-svn: 21345
2005-04-19 04:32:54 +00:00
Nate Begeman
3b1c0df702
Next round of PPC CR optimizations. For the following code:
...
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
2005-04-18 07:48:09 +00:00
Nate Begeman
85cd65b389
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
llvm-svn: 21314
2005-04-18 02:43:24 +00:00
Chris Lattner
a1fd64a073
Handle ExternalSymbol operands in the PPC JIT
...
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
Nate Begeman
ecb5b5c028
Make pattern isel default for ppc
...
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
2005-04-15 22:12:16 +00:00
Nate Begeman
604895b03c
Implement multi-way branches through logical ops on condition registers.
...
This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
llvm-svn: 21298
2005-04-14 09:45:08 +00:00
Nate Begeman
b707ec16b4
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
llvm-svn: 21295
2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56
Start allocating condition registers. Almost all explicit uses of CR0 are
...
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
llvm-svn: 21294
2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
...
where it is safe to do so.
llvm-svn: 21293
2005-04-13 22:14:14 +00:00
Nate Begeman
20b3399465
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
llvm-svn: 21291
2005-04-13 21:23:31 +00:00
Chris Lattner
8489ac991d
remove one more occurance of this that snuck in
...
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
Chris Lattner
26c7c9150a
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
2005-04-13 02:40:26 +00:00
Nate Begeman
a56527ea5f
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
llvm-svn: 21260
2005-04-12 21:22:28 +00:00