1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 08:23:21 +01:00
Commit Graph

62139 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
4731169504 Move non-temporal movs to their own section
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
Bob Wilson
be81c92b41 Add support for encoding NEON VMOV (from core register to scalar) instructions.
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167
2010-06-29 17:34:07 +00:00
Bruno Cardoso Lopes
2dca1dd168 Add sqrt, rsqrt and rcp AVX instructions
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
Jim Grosbach
151bec3c2d skip dbg_value instructions
llvm-svn: 107154
2010-06-29 16:55:24 +00:00
Gabor Greif
6ecf606379 minor cosmetics
llvm-svn: 107148
2010-06-29 16:27:38 +00:00
Bob Wilson
74996289e3 The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147
2010-06-29 16:25:11 +00:00
Gabor Greif
c84c81085c use ArgOffset constant to prepare for operand rotation
llvm-svn: 107146
2010-06-29 16:21:20 +00:00
Gabor Greif
50741043d0 use ArgOperand API
llvm-svn: 107145
2010-06-29 16:17:26 +00:00
Gabor Greif
e82ec778a2 use ArgOperand API
llvm-svn: 107144
2010-06-29 16:01:30 +00:00
Duncan Sands
2f42c8716a Return Changed. This required setting Changed if dbg metadata
is stripped off.  Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.

llvm-svn: 107142
2010-06-29 14:52:10 +00:00
Duncan Sands
07e9b76b61 It seems clear that this should return Changed.
llvm-svn: 107141
2010-06-29 14:49:35 +00:00
Rafael Espindola
832e4ddde7 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140
2010-06-29 14:02:34 +00:00
Duncan Sands
8876fd487d getMachineBasicBlockAddress returns a uintptr_t - don't truncate
to unsigned only to extend back to a pointer sized value on the
next line.

llvm-svn: 107139
2010-06-29 13:34:20 +00:00
Duncan Sands
84321cc550 The variable ValueSize is set to 1 on both code paths, and then
ignored!  Remove it.

llvm-svn: 107138
2010-06-29 13:30:08 +00:00
Duncan Sands
5446bab8a5 The variable "Value" is carefully set to Layout.getSymbolAddress,
but then not actually used - maybe a bug?  Remove the variable.

llvm-svn: 107137
2010-06-29 13:26:33 +00:00
Duncan Sands
78f0758143 Remove unused calls to Lexer.getLoc and the pointless variable HasFillExpr.
llvm-svn: 107136
2010-06-29 13:24:40 +00:00
Duncan Sands
1a45e3dbce Remove pointless variable LastDef.
llvm-svn: 107135
2010-06-29 13:23:22 +00:00
Duncan Sands
4869e2b3f7 Looks like this test is missing an XFAIL line.
llvm-svn: 107134
2010-06-29 13:18:50 +00:00
Duncan Sands
9eff796264 Remove unused variable Loc and pointless variables unified_syntax
and thumb_mode.

llvm-svn: 107133
2010-06-29 13:04:35 +00:00
Gabor Greif
d4fc146cb3 use ArgOperand APIs
llvm-svn: 107132
2010-06-29 13:03:46 +00:00
Duncan Sands
25a2d02c5c Remove an unused and a pointless variable.
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
Duncan Sands
aecd43c04e Remove pointless and unused variables.
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
Gabor Greif
3c768ce3f0 encode operand initializations (at fixed index)
in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.

llvm-svn: 107129
2010-06-29 11:41:38 +00:00
Duncan Sands
b367b1e428 Remove a pointless variable.
llvm-svn: 107128
2010-06-29 11:39:45 +00:00
Duncan Sands
b955b3bf92 Remove initialized but otherwise unused variables.
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
Duncan Sands
d0286618b5 Remove variables that are written by not read.
llvm-svn: 107126
2010-06-29 11:07:47 +00:00
Benjamin Kramer
acb45b427b Use a more obvious way to avoid compiling functions which are only used when XDEBUG is enabled.
llvm-svn: 107125
2010-06-29 10:03:11 +00:00
Chandler Carruth
e9bf8c4ee8 Jump through some silly hoops to make GCC accept that a function may not always
be called.

llvm-svn: 107124
2010-06-29 06:46:00 +00:00
Evan Cheng
6349fa5ec4 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
Evan Cheng
9883684f03 Change if-cvt options to something that actually as useable.
llvm-svn: 107121
2010-06-29 05:37:59 +00:00
Jim Grosbach
aed0823a7c When processing loops for scheduling latencies (used for live outs on loop
back-edges), make sure not to include dbg_value instructions in the count.
Closing in on the end of rdar://7797940

llvm-svn: 107119
2010-06-29 04:48:13 +00:00
Dan Gohman
f5dfb360be Just as its not safe to blindly transfer the nsw bit from an add
instruction to an add scev, it's not safe to blindly transfer the
inbounds flag from a gep instruction to an nsw on the scev for the
gep.

llvm-svn: 107117
2010-06-29 01:41:41 +00:00
Bruno Cardoso Lopes
1fe3ed0e67 Refactoring of arithmetic instruction classes with unary operator
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
Jakob Stoklund Olesen
b72b136170 When no memoperands are present, assume unaligned, volatile.
llvm-svn: 107114
2010-06-29 01:13:07 +00:00
Bill Wendling
e4647a0983 Strip resulting binaries.
llvm-svn: 107112
2010-06-29 01:08:57 +00:00
Bob Wilson
674598a72c Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:

1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch.  Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).

The change relative to the previous patch is:

@@ -1036,10 +1036,6 @@
     IterIfcvt = false;
   }
 
-  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
-  // which is typically the case for IfConvertSimple, so explicitly remove
-  // CvtBBI as a successor.
-  BBI.BB->removeSuccessor(CvtBBI->BB);
   RemoveExtraEdges(BBI);
 
   // Update block info. BB can be iteratively if-converted.


2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised.  The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond.  I added the following change to check for
that:

@@ -1276,7 +1276,18 @@
   // tail, add a unconditional branch to it.
   if (TailBB) {
     BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
-    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+    bool CanMergeTail = !TailBBI.HasFallThrough;
+    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+    // check if there are any other predecessors besides those.
+    unsigned NumPreds = TailBB->pred_size();
+    if (NumPreds > 1)
+      CanMergeTail = false;
+    else if (NumPreds == 1 && CanMergeTail) {
+      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+      if (*PI != BBI1->BB && *PI != BBI2->BB)
+        CanMergeTail = false;
+    }
+    if (CanMergeTail) {
       MergeBlocks(BBI, TailBBI);
       TailBBI.IsDone = true;
     } else {

With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.

llvm-svn: 107110
2010-06-29 00:55:23 +00:00
Dan Gohman
37bf33ccff Add an Intraprocedural form of BasicAliasAnalysis, which aims to
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.

llvm-svn: 107109
2010-06-29 00:50:39 +00:00
Bruno Cardoso Lopes
e4809f15bf Described the missing AVX forms of SSE2 convert instructions
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
Bob Wilson
2a4e6d0e34 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107
2010-06-29 00:26:13 +00:00
Devang Patel
9762137bd4 The comment string does not match for all targets. PowerPC uses ;.
llvm-svn: 107103
2010-06-29 00:04:40 +00:00
Bob Wilson
5ae34cf120 Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

llvm-svn: 107097
2010-06-28 23:40:25 +00:00
Dale Johannesen
b80bbb4666 Refix XTARGET. Previous attempt matches on powerpc-apple-darwin,
although I don't see why.

llvm-svn: 107090
2010-06-28 22:45:33 +00:00
Dale Johannesen
aed6ab0261 Attempt to fix XTARGET.
llvm-svn: 107088
2010-06-28 22:31:52 +00:00
Bob Wilson
aee90dacaa Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.

llvm-svn: 107086
2010-06-28 22:23:17 +00:00
Devang Patel
2c43f47ccc Use DW_FORM_addr for DW_AT_entry_pc.
llvm-svn: 107085
2010-06-28 22:22:47 +00:00
Dan Gohman
ccdfbe251d Add a blurb about -scev-aa.
llvm-svn: 107080
2010-06-28 22:09:52 +00:00
Dale Johannesen
94738aa18e In asm's, output operands with matching input constraints
have to be registers, per gcc documentation.  This affects
the logic for determining what "g" should lower to.  PR 7393.
A couple of existing testcases are affected.

llvm-svn: 107079
2010-06-28 22:09:45 +00:00
Kevin Enderby
aaad4f57f0 Added the darwin .secure_log_unique and .secure_log_reset directives.
llvm-svn: 107077
2010-06-28 21:45:58 +00:00
Dan Gohman
50fffcaea3 Constant fold x == undef to undef.
llvm-svn: 107074
2010-06-28 21:30:07 +00:00
Jim Grosbach
8441e67098 tidy up style. no functional change.
llvm-svn: 107073
2010-06-28 21:29:17 +00:00