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19615 Commits

Author SHA1 Message Date
Bill Wendling
aea682a6fe Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00
David Meyer
c50cb2f15a Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Joe Abbey
cebf5dc822 Commit test, capitalizing store... keep it simple. 
llvm-svn: 142336
 2011-10-18 04:44:36 +00:00
Eli Friedman
f43710f4a8 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Lang Hames
dfb145da26 Backing out patch. Will refactor to remove the AsmParser dependency on Target. 
llvm-svn: 142323
 2011-10-18 00:23:49 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Lang Hames
4370882b22 Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies. 
Thanks to Raphael Espindola for tracking down the CMake issues.

llvm-svn: 142306
 2011-10-17 23:24:48 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Nick Lewycky
c551c1c5f9 Add support for a new extension to the .file directive: 
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
 2011-10-17 23:05:28 +00:00
Chad Rosier
ef5ee1892c Add a few FIXME comments. 
llvm-svn: 142299
 2011-10-17 22:54:23 +00:00
Jim Grosbach
8e9ca16af6 Tidy up. 
llvm-svn: 142297
 2011-10-17 22:41:42 +00:00
Rafael Espindola
a40b412c70 142288 broke the build: 
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)

Revert "Validate target data layout strings."

This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.

llvm-svn: 142296
 2011-10-17 22:37:51 +00:00
Bill Wendling
8390d96c1a Now Igor, throw the switch...give my creation life! 
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>

llvm-svn: 142294
 2011-10-17 22:26:23 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Lang Hames
416d4f3f36 Validate target data layout strings. 
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.

llvm-svn: 142288
 2011-10-17 22:05:34 +00:00
Benjamin Kramer
bc2d3cbf7e Use a SmallVector for intrinsic argument types. 
llvm-svn: 142259
 2011-10-17 21:33:26 +00:00
Bill Wendling
8f01b6c71d Don't renumber the blocks here. This could cause problems later on if another 
pass renumbers the blocks again.

llvm-svn: 142258
 2011-10-17 21:32:56 +00:00
Cameron Zwarich
4f62e0c1e3 Pseudoinstructions should not be less constrained than the instruction they are 
lowered to. This fixes a lot of verifier failures on the test suite.

llvm-svn: 142254
 2011-10-17 21:20:13 +00:00
Jim Grosbach
eeb05f7532 Tidy up organization. 
llvm-svn: 142248
 2011-10-17 21:00:11 +00:00
Bill Wendling
5d4f239d0a Add a call to EmitSjLjDispatchBlock. 
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.

llvm-svn: 142245
 2011-10-17 20:37:20 +00:00
Jim Grosbach
22167dc73c Fix improperly formed assert() call. 
llvm-svn: 142239
 2011-10-17 20:22:59 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Hal Finkel
f61af0e4b0 Revert change to function alignment b/c existing logic was fine 
llvm-svn: 142224
 2011-10-17 18:53:03 +00:00
Chad Rosier
8247682aba Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223
 2011-10-17 18:48:30 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
9045499a59 Revert change made in r142205. 
llvm-svn: 142217
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
0ab0d4d1f4 Redefine count-leading 0s and 1s instructions. 
llvm-svn: 142216
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
f81b089ac3 Redefine mfhi/lo and mthi/lo instructions. 
llvm-svn: 142214
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
4243d8876b Redefine multiply and divide instructions. 
llvm-svn: 142211
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
6b17ee5b50 Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
 2011-10-17 18:17:58 +00:00
Hal Finkel
df4af2dd0b Remove >80-col line and unicode 
llvm-svn: 142209
 2011-10-17 18:10:08 +00:00
Akira Hatanaka
3b8c93eda7 Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
82a1bab4ab Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
llvm-svn: 142205
 2011-10-17 18:01:00 +00:00
Michael J. Spencer
7ce30d63fd Fix CMake build. 
llvm-svn: 142204
 2011-10-17 17:50:39 +00:00
Devang Patel
8f9c569a13 svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp 
There is no reason to have simple IR level pass in lib/Target.

llvm-svn: 142200
 2011-10-17 17:17:43 +00:00
Hal Finkel
f5b7d5ea68 Instructions for Book E PPC should be word aligned, set function alignment to reflect this 
llvm-svn: 142194
 2011-10-17 17:01:41 +00:00
Craig Topper
29c4a473d0 Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. 
llvm-svn: 142177
 2011-10-17 05:33:10 +00:00
Bill Wendling
76b62805ac Add comment explaining that the order of processing doesn't matter here. 
llvm-svn: 142176
 2011-10-17 05:25:09 +00:00
Hal Finkel
b128cda81b Add PPC 440 scheduler and some associated tests (new files) 
llvm-svn: 142171
 2011-10-17 04:03:55 +00:00
Hal Finkel
74543873a4 Add PPC 440 scheduler and some associated tests 
llvm-svn: 142170
 2011-10-17 04:03:49 +00:00
Craig Topper
6c900d9810 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Benjamin Kramer
3fed5faf01 Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing. 
<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

llvm-svn: 142137
 2011-10-16 12:10:27 +00:00
Benjamin Kramer
2119dc8df2 X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands. 
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

llvm-svn: 142135
 2011-10-16 11:28:29 +00:00
Nadav Rotem
a733f43137 Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was 
no pattern.

llvm-svn: 142130
 2011-10-16 10:02:06 +00:00
Craig Topper
2cd868184c Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
91b4292682 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Cameron Zwarich
f4cddde4e1 Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. 
These missing flags show up as errors when running -verify-coalescing on
test-suite.

llvm-svn: 142111
 2011-10-16 06:38:10 +00:00
Cameron Zwarich
b3429a24c3 Fix an obvious typo found when looking at nearby code. 
llvm-svn: 142110
 2011-10-16 06:38:06 +00:00
Chris Lattner
321335142c Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper
4c6357d4af Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper
dab0c92a4f Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
llvm-svn: 142089
 2011-10-16 00:21:51 +00:00
Craig Topper
62e63d9bb9 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Nadav Rotem
a623eb2a7d The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements. 
llvm-svn: 142081
 2011-10-15 20:05:17 +00:00
Nadav Rotem
6906c738f3 ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements. 
llvm-svn: 142080
 2011-10-15 20:03:12 +00:00
Benjamin Kramer
2b5e0cc68a SmallVector -> array 
llvm-svn: 142073
 2011-10-15 13:28:31 +00:00
Jakob Stoklund Olesen
b0f487f367 Mark tADDrSPi as having side effects again. 
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations.  I am guessing that it got
moved across a stack pointer update.

Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.

llvm-svn: 142030
 2011-10-15 00:57:13 +00:00
Chad Rosier
42a60003a1 Thumb1 does not support dynamic stack realignment. 
rdar://10288916 is tracking this fix.

In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment.  Lang's work now
prevents this from happening (LLVM commit r141599).  Now that this really 
shouldn't happen report a fatal error rather than silently generate bad code.

llvm-svn: 142028
 2011-10-15 00:28:24 +00:00
Bill Wendling
bff30bb463 Mark registers as DEAD because they're really just clobbers. 
llvm-svn: 142027
 2011-10-15 00:27:44 +00:00
Eli Friedman
c8d798d91e Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. 
llvm-svn: 142022
 2011-10-14 23:58:49 +00:00
Bill Wendling
b1bbf0394f Make sure that the register is in the register class before adding it as a machine op. 
llvm-svn: 142021
 2011-10-14 23:55:44 +00:00
Bill Wendling
4191045be4 Mark the invoke call instruction as implicitly defining the callee-saved registers. 
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.

llvm-svn: 142018
 2011-10-14 23:34:37 +00:00
Richard Trieu
5370a1ef01 Fix a non-firing assert. Change: 
assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000
 2011-10-14 20:50:26 +00:00
Evan Cheng
15ab434f80 A few 80-col violations. 
llvm-svn: 141988
 2011-10-14 20:36:23 +00:00
Hal Finkel
8e97422bd9 Add an implementation of the CanLowerReturn function to the PPC backend 
llvm-svn: 141981
 2011-10-14 19:51:36 +00:00
Akira Hatanaka
e4597ae8c1 Add f128 to datalayout string. 
llvm-svn: 141978
 2011-10-14 19:14:50 +00:00
Hal Finkel
a298e1cae7 initial test commit (remove whitespace) 
llvm-svn: 141972
 2011-10-14 18:54:13 +00:00
Akira Hatanaka
70199b7136 Revert r141932, r141936 and r141937. 
llvm-svn: 141959
 2011-10-14 17:16:39 +00:00
Craig Topper
0a11eb1b21 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper
6b2120a8e1 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Akira Hatanaka
24e913fbe2 Definition of function getMipsRegisterNumbering. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141938
 2011-10-14 03:04:24 +00:00
Akira Hatanaka
516b4b0352 Add definition of class MipsELFWriterInfo. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141937
 2011-10-14 02:55:47 +00:00
Akira Hatanaka
9922f8d014 Add missing relocation types. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141936
 2011-10-14 02:47:50 +00:00
Akira Hatanaka
b1ede8157d Fixup enumerations. 
Patch by Jack Carter at Mips. 

llvm-svn: 141934
 2011-10-14 02:38:56 +00:00
Akira Hatanaka
a5d655b991 Add more Mips relocation types. 
Patch by Jack Carter at Mips. 

llvm-svn: 141932
 2011-10-14 02:17:30 +00:00
Jakob Stoklund Olesen
a31553dbf7 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929
 2011-10-14 01:00:49 +00:00
Jakob Stoklund Olesen
d7827f928d V_SET0 has no side effects. 
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

llvm-svn: 141924
 2011-10-14 00:39:50 +00:00
Eli Friedman
94373219c3 Fix undefined shift. Patch by Ahmed Charles. 
llvm-svn: 141914
 2011-10-13 23:36:06 +00:00
Eli Friedman
d1174d008e Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles. 
llvm-svn: 141912
 2011-10-13 23:27:48 +00:00
Eli Friedman
219f1841f7 Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles. 
llvm-svn: 141909
 2011-10-13 23:13:35 +00:00
Eli Friedman
74b48114e3 Simplify and avoid undefined shift. Based on patch by Ahmed Charles. 
llvm-svn: 141903
 2011-10-13 22:40:23 +00:00
Owen Anderson
9f90e2252c SETEND is not allowed in an IT block. 
llvm-svn: 141874
 2011-10-13 17:58:39 +00:00
Kalle Raiskila
15993a5d28 Mark 'branch indirect' instruction as an indirect branch. 
Not having it confused assembly printing of jumptables.

llvm-svn: 141862
 2011-10-13 11:40:03 +00:00
Bill Wendling
dcd9c25744 More closely follow libgcc, which has code after the `ret' instruction to 
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859
 2011-10-13 08:24:19 +00:00
Bill Wendling
2a571af745 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Bill Wendling
a6bf25f30a Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. 
llvm-svn: 141856
 2011-10-13 07:42:32 +00:00
Craig Topper
eb29e18c9b Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Craig Topper
0d25fa802f Add 'implicit EFLAGS' to patterns for popcnt and lzcnt 
llvm-svn: 141853
 2011-10-13 06:18:52 +00:00
Jim Grosbach
b9dddb0d13 ARM addrmode5 represents the 'U' bit of the encoding backwards. 
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819
 2011-10-12 21:59:02 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
71dbc175ce addrmode2 is gone from these, so no need for the reg0 operand. 
llvm-svn: 141794
 2011-10-12 18:11:24 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Jim Grosbach
70a91e2da7 80 columns. 
llvm-svn: 141781
 2011-10-12 16:36:01 +00:00
Jim Grosbach
3b205dab2d Tidy up. Formatting. 
llvm-svn: 141780
 2011-10-12 16:34:37 +00:00
Akira Hatanaka
68c6bb2c02 Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
llvm-svn: 141761
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
08230e45e0 Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.

llvm-svn: 141757
 2011-10-12 00:56:06 +00:00
Nick Lewycky
e2234c564a Fix indent in comment. 
llvm-svn: 141749
 2011-10-12 00:14:12 +00:00
Jakob Stoklund Olesen
2611cc2520 Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746
 2011-10-12 00:06:23 +00:00
Akira Hatanaka
ab6aae33e9 Change name of class to ArithOverflowR. 
llvm-svn: 141743
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
5273f6aabb Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.

llvm-svn: 141742
 2011-10-11 23:38:52 +00:00
Akira Hatanaka
0d687917ae Fix comment. 
llvm-svn: 141737
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
12da673e60 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
 2011-10-11 23:05:46 +00:00
Akira Hatanaka
8a43300a4f Fix function isUnalignedLoadStore. 
llvm-svn: 141722
 2011-10-11 22:04:01 +00:00
Jim Grosbach
d2cfc2b31f ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Akira Hatanaka
4ea17fffd6 Remove unused PatLeaf. 
llvm-svn: 141720
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
99550c035f Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.

llvm-svn: 141718
 2011-10-11 21:48:01 +00:00
Bill Wendling
a1c238d8bf Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
llvm-svn: 141716
 2011-10-11 21:40:47 +00:00
Akira Hatanaka
7ae83fe86a Remove redundancy in setcc patterns using multiclass. 
llvm-svn: 141715
 2011-10-11 21:40:01 +00:00
Akira Hatanaka
f8aabd951e Use sltiu instead of sltu when a register operand and immediate are compared. 
llvm-svn: 141708
 2011-10-11 20:44:43 +00:00
Jim Grosbach
66bf42f4bb ARM addressing mode cleanup for LDC/STC. 
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

llvm-svn: 141704
 2011-10-11 20:17:35 +00:00
Akira Hatanaka
27c0f84dce Add patterns for conditional branches with 64-bit register operands. 
llvm-svn: 141696
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
1594be76f8 Add support for 64-bit set-on-less-than instructions. 
llvm-svn: 141695
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
9df92e48e1 Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Jim Grosbach
a4d00441c7 ARM parse alignment specifier for NEON load/store instructions. 
llvm-svn: 141682
 2011-10-11 17:29:55 +00:00
Jim Grosbach
556c9f6f6c ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. 
llvm-svn: 141671
 2011-10-11 15:59:20 +00:00
Richard Osborne
ca9b871ab7 Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks. 
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).

llvm-svn: 141666
 2011-10-11 12:55:35 +00:00
Kalle Raiskila
19b09a39e2 Fix a iterator out of bounds error, that triggers rarely. 
llvm-svn: 141665
 2011-10-11 12:55:18 +00:00
Craig Topper
881d972428 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. 
llvm-svn: 141656
 2011-10-11 07:13:09 +00:00
Craig Topper
db2d702bff Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
llvm-svn: 141654
 2011-10-11 07:01:37 +00:00
Craig Topper
c498c5c0e6 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Craig Topper
7ae42fbd7e Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Akira Hatanaka
20808df5a0 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Jakob Stoklund Olesen
81dd697279 Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). 
The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

llvm-svn: 141619
 2011-10-11 00:59:06 +00:00
Akira Hatanaka
3f89f9bc37 Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Lang Hames
41b4ff724d Fixed natural stack alignment for Linux x86-32. Thanks Eli. 
llvm-svn: 141616
 2011-10-11 00:51:36 +00:00
Akira Hatanaka
1913a9abc0 Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
llvm-svn: 141615
 2011-10-11 00:44:20 +00:00
Akira Hatanaka
6f90f8d68d Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
llvm-svn: 141613
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
404fb72f59 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka
ac95006d45 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Bill Wendling
1a1ee723b0 Simplify check that optional def is there and is CPSR. 
llvm-svn: 141602
 2011-10-11 00:10:41 +00:00
Lang Hames
be4997db2f Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.

llvm-svn: 141599
 2011-10-10 23:42:08 +00:00
Jim Grosbach
ab5dbe090b Simplify operand Kind checks a bit. 
llvm-svn: 141592
 2011-10-10 23:06:42 +00:00
Bill Wendling
7121342ad5 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Jim Grosbach
21a08a2b41 Add a name to sub-operand for clarity. 
llvm-svn: 141590
 2011-10-10 22:55:05 +00:00
Bill Wendling
9cf46b3bd5 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>

llvm-svn: 141589
 2011-10-10 22:52:53 +00:00
Eli Friedman
7188ba35cb Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Benjamin Kramer
60387b6640 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
llvm-svn: 141571
 2011-10-10 19:35:07 +00:00
Nadav Rotem
38187aec17 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Benjamin Kramer
c498279bec X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
llvm-svn: 141563
 2011-10-10 18:34:56 +00:00
Bill Wendling
7cba44defc Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Bill Wendling
94258753c7 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
 2011-10-10 07:24:23 +00:00
Craig Topper
251bbfb1f7 Put a bunch of calls to ToggleFeature behind proper if statements. 
llvm-svn: 141527
 2011-10-10 05:34:02 +00:00
Chad Rosier
2fc181986a Fix a regression from r138445. If we're loading from the frame/base pointer 
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

llvm-svn: 141523
 2011-10-10 01:03:35 +00:00
Justin Holewinski
ce14c646cd PTX: Print .ptr kernel attributes if PTX version >= 2.2 
llvm-svn: 141508
 2011-10-09 15:42:02 +00:00
Craig Topper
9b7ab95570 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
d94788edb9 Prevent potential NOREX bug. 
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500
 2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen
b49557d06d Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
 2011-10-08 18:28:28 +00:00
Nicolas Geoffray
8c7ad22407 Always check if a method or a type exist before trying to create it. 
llvm-svn: 141490
 2011-10-08 11:56:36 +00:00
Anton Korobeynikov
b0534f0113 Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. 
llvm-svn: 141481
 2011-10-08 08:38:45 +00:00
Akira Hatanaka
4a78bb776f Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00