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Commit Graph

210485 Commits

Author SHA1 Message Date
Kazu Hirata
ab8cd6c8fd [llvm] Use isa instead of dyn_cast (NFC) 2021-01-29 23:23:37 -08:00
Kazu Hirata
95dfb94fbd [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-29 23:23:36 -08:00
Kazu Hirata
04422f73a1 [llvm] Use append_range (NFC) 2021-01-29 23:23:34 -08:00
Yang Fan
065bbe82a5 [NFC][VFS] Fix a build warning due to an extra semicolon 2021-01-30 14:52:43 +08:00
Greg McGary
286fe0725a [llvm-objdump-macho] print per-second-level-page encodings for option --unwind-info
Compact unwind entries have 8 bits for the encoding-table offset:
* offsets 0..126 reference the global commmon-encodings table, while
* offsets 127..255 reference a per-second-level-page table.
This diff teaches `llvm-objdump` to print this per-page encodings table.

Differential Revision: https://reviews.llvm.org/D93265
2021-01-29 21:59:07 -07:00
Wang, Pengfei
53516796c3 [X86] Fix tile config register spill issue.
This is an optimized approach for D94155.

Previous code build the model that tile config register is the user of
each AMX instruction. There is a problem for the tile config register
spill. When across function, the ldtilecfg instruction may be inserted
on each AMX instruction which use tile config register. This cause all
tile data register clobber.

To fix this issue, we remove the model of tile config register. Instead,
we analyze the AMX instructions between one call to another. We will
insert ldtilecfg after the first call if we find any AMX instructions.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D95136
2021-01-30 12:53:57 +08:00
Sriraman Tallam
e880bbaf88 Detect Source Drift with Propeller.
Source Drift happens when the sources are updated after profiling the binary
but before building the final optimized binary. If the source has changed since
the profiles were obtained, optimizing basic blocks might be sub-optimal. This
only applies to BasicBlockSection::List as it creates clusters of basic blocks
using basic block ids. Source drift can invalidate these groupings leading to
sub-optimal code generation with regards to performance.

PGO source drift for a particular function can be detected using function
metadata added in D95495.

When source drift is deected, disable basic block clusters by default
which can be re-enabled with  -mllvm option
bbsections-detect-source-drift=false.

Differential Revision: https://reviews.llvm.org/D95593
2021-01-29 18:47:26 -08:00
Craig Topper
8aef3111a6 [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
The IR and CHECK lines are identical so just keep one copy.
2021-01-29 17:32:08 -08:00
Nathan Hawes
3567e63d35 [VFS] Combine VFSFromYamlDirIterImpl and OverlayFSDirIterImpl into a single implementation (NFC)
As a fixme notes, both of these directory iterator implementations are
conceptually similar and duplicate the functionality of returning and uniquing
entries across two or more directories. This patch combines them into a single
class 'CombiningDirIterImpl'.

This also drops the 'Redirecting' prefix from RedirectingDirEntry and
RedirectingFileEntry to save horizontal space. There's no loss of clarity as
they already have to be prefixed with 'RedirectingFileSystem::' whenever
they're referenced anyway.

rdar://problem/72485443
Differential Revision: https://reviews.llvm.org/D94857
2021-01-30 11:10:10 +10:00
Hsiangkai Wang
c25fba26b5 [RISCV] Update the version number to v0.10 for vector. 2021-01-30 07:55:58 +08:00
Hsiangkai Wang
ed9aa7c2f8 [RISCV] Update the version number to v0.10 for vector.
v0.10 is tagged in V specification. Update the version to v0.10.

Differential Revision: https://reviews.llvm.org/D95680
2021-01-30 07:20:05 +08:00
Hsiangkai Wang
6f75576518 [NFC][RISCV] Remove redundant pseudo instructions for vector load/store.
Not all combinations of SEW and LMUL we need to support. For example, we
only need to support [M1, M2, M4, M8] for SEW = 64. There is no need to
define pseudos for PseudoVLSE64MF8, PseudoVLSE64MF4, and PseudoVLSE64MF2.

Differential Revision: https://reviews.llvm.org/D95667
2021-01-30 07:20:05 +08:00
Stanislav Mekhanoshin
cea4122bba [AMDGPU] Be more specific in needsFrameBaseReg
A condition "mayLoadOrStore" is too broad for that function.

Differential Revision: https://reviews.llvm.org/D95700
2021-01-29 14:40:25 -08:00
Roman Lebedev
f23effe39b [ExpandMemCmpPass] Preserve Dominator Tree, if available
This finishes getting rid of all the avoidable Dominator Tree recalculations
in X86 optimized codegen pipeline.
2021-01-30 01:14:51 +03:00
Roman Lebedev
e695f6dc77 [ShadowStackGCLowering] Preserve Dominator Tree, if avaliable
This doesn't help avoid any Dominator Tree recalculations just yet,
there's one more pass to go..
2021-01-30 01:14:51 +03:00
Roman Lebedev
c44a23a91c [LowerConstantIntrinsics] Preserve Dominator Tree, if avaliable 2021-01-30 01:14:50 +03:00
Christopher Tetreault
67f2871ba2 [SVE] delete VectorType::getNumElements()
The previously agreed-upon deprecation period for
VectorType::getNumElements() has passed. This patch removes this method
and completes the refactor proposed in the RFC:
https://lists.llvm.org/pipermail/llvm-dev/2020-March/139811.html

Reviewed By: david-arm, rjmccall

Differential Revision: https://reviews.llvm.org/D95570
2021-01-29 13:46:54 -08:00
Sriraman Tallam
684c703600 Emit metadata when instr. profiles hash mismatch occurs.
This patch emits "instr_prof_hash_mismatch" function annotation metadata if
there is a hash mismatch while applying instrumented profiles.

During the PGO optimized build using instrumented profiles, if the CFG of
the function has changed since generating the profile, a hash mismatch is
encountered. This patch emits this information as annotation metadata. We
plan to use this with Propeller which is done at the machine IR level.
Propeller is usually applied on top of PGO and a hash mismatch during
PGO could be used to detect source drift.

Differential Revision: https://reviews.llvm.org/D95495
2021-01-29 12:56:01 -08:00
Christopher Tetreault
04767b59b5 Revert "[CMake] Actually require python 3.6 or greater"
There are builders that do not have python 3.6. Revert until this situation can be rectified

This reverts commit 0703b0753c40dad30f1683403f6600bd2cb42055.
2021-01-29 12:03:32 -08:00
Christopher Tetreault
9d92cc60ea [CMake] Actually require python 3.6 or greater
Previously, CMake would find any version of Python3. However, the project
claims to require 3.6 or greater, and 3.6 features are being used.

Reviewed By: yln

Differential Revision: https://reviews.llvm.org/D95635
2021-01-29 11:47:21 -08:00
Jessica Paquette
cc9fc9bbc4 [GlobalISel] Remove hint instructions in generic InstructionSelect code.
I think every target will want to remove these in the same way. Rather than
making them all implement the same code, let's just put this in
InstructionSelect.

Differential Revision: https://reviews.llvm.org/D95652
2021-01-29 11:20:07 -08:00
Fangrui Song
c0933fb949 [VE] Add include for formatted_raw_ostream after 046cfb856517c6140d5e1c0989232e26d00b05b2 2021-01-29 11:18:30 -08:00
Jay Foad
9fb7df77ee [GlobalISel] Fix modifying a G_OR without notifying the observer
Remove the call to setFlags in favour of creating the instruction with
the correct flags in the first place, so we don't have to explicitly
notify the observer.

Differential Revision: https://reviews.llvm.org/D95681
2021-01-29 16:32:24 +00:00
Jay Foad
8d43ed5df7 [AMDGPU] Test all register names known to AMDGPUPALMetadata
Differential Revision: https://reviews.llvm.org/D95684
2021-01-29 16:16:26 +00:00
J-Y You
3d86bcfc2f [TableGen] Fix instantiating multiclass in foreach
If multiclass argument comes from loop varaible and argument is record type,
it will not recognize the type. This patch ensures that loop variables are
resolved correctly.

Differential Revision: https://reviews.llvm.org/D95308
2021-01-29 10:25:33 -05:00
Simon Pilgrim
83ad183af3 [X86][SSE] combineExtractWithShuffle - support zero-extending to allow extracting from narrow shuffle masks
If the shuffle mask can't be widened to match the original extracted element width, see if the upper bits are zeroable - which allows us to extract+zero-extend the smaller extraction.
2021-01-29 14:22:10 +00:00
Sjoerd Meijer
0c18639b63 [MachineLICM] Fix wrong and confusing comment. NFC. 2021-01-29 13:39:07 +00:00
Nico Weber
b2ad6dcaa3 [gn build] port e90e455d2a0cc 2021-01-29 08:36:19 -05:00
Abhina Sreeskantharajan
8fb00b74f1 [test] Use host platform specific error message substitution in lit tests
On z/OS, the following error message is not matched correctly in lit tests.

```
EDC5129I No such file or directory.
```

This patch uses a lit config substitution to check for platform specific error messages.

Reviewed By: muiez, jhenderson

Differential Revision: https://reviews.llvm.org/D95246
2021-01-29 07:16:30 -05:00
Nikita Popov
5b26973941 [MemCpyOpt] Add test for incorrect optimization across lifetime (NFC)
This only affects the MemorySSA-based implementation.
2021-01-29 12:57:02 +01:00
Florian Hahn
f1e4600eb5 [LTO] Update splitCodeGen to take a reference to the module. (NFC)
splitCodeGen does not need to take ownership of the module, as it
currently clones the original module for each split operation.

There is an ~4 year old fixme to change that, but until this is
addressed, the function can just take a reference to the module.

This makes the transition of LTOCodeGenerator to use LTOBackend a bit
easier, because under some circumstances, LTOCodeGenerator needs to
write the original module back after codegen.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D95222
2021-01-29 11:53:11 +00:00
Nico Weber
8b8c200116 [gn build] (semi-manually) port 2ff8662b5d16 2021-01-29 06:48:17 -05:00
Rafik Zurob
b5e924f8cd [llvm-jitlink] Replace use of deprecated gethostbyname by getaddrinfo.
This patch replaces use of deprecated gethostbyname by getaddrinfo.

Author: Rafik Zurob

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D95477
2021-01-29 03:11:16 -06:00
Georgii Rymar
a153345c4f [llvm-readobj/elf] - Report "bitcode files are not supported" warning for bitcode files.
Fixes https://bugs.llvm.org/show_bug.cgi?id=43543

Currently we report "The file was not recognized as a valid object file" for BC files.
Also, we terminate dumping.

Instead we could report a better warning and try to continue dumping other files.
This is what this patch implements.

Differential revision: https://reviews.llvm.org/D95605
2021-01-29 12:04:41 +03:00
Yang Fan
d1398bbcf7 [NFC][ScalarizeMaskedMemIntrin] Fix unused variable warning
GCC warning:
```
/llvm-project/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp: In function ‘void scalarizeMaskedStore(llvm::CallInst*, llvm::DomTreeUpdater*, bool&)’:
/llvm-project/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp:295:15: warning: variable ‘IfBlock’ set but not used [-Wunused-but-set-variable]
  295 |   BasicBlock *IfBlock = CI->getParent();
      |               ^~~~~~~
/llvm-project/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp: In function ‘void scalarizeMaskedScatter(llvm::CallInst*, llvm::DomTreeUpdater*, bool&)’:
/llvm-project/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp:555:15: warning: variable ‘IfBlock’ set but not used [-Wunused-but-set-variable]
  555 |   BasicBlock *IfBlock = CI->getParent();
      |               ^~~~~~~
```
2021-01-29 15:15:58 +08:00
Kazu Hirata
537d9c3aa6 [MustExecute] Use ListSeparator (NFC) 2021-01-28 22:21:16 -08:00
Kazu Hirata
425d87c917 [llvm] Populate SmallVector at construction time (NFC) 2021-01-28 22:21:14 -08:00
Kazu Hirata
606fed8845 [llvm] Forward-declare formatted_raw_ostream (NFC)
Various *TargetStreamer.h need formatted_raw_ostream but rely on a
forward declaration of formatted_raw_ostream in MCStreamer.h.  This
patch adds forward declarations right in *TargetStreamer.h.

While we are at it, this patch removes the one in MCStreamer.h, where
it is unnecessary.
2021-01-28 22:21:13 -08:00
Wei Mi
034d6b415f [LiveDebugVariables] Add cache for SkipPHIsLabelsAndDebug to prevent
iterating the same PHI/LABEL/Debug instructions repeatedly.

We run into a compiling timeout problem when building a target after its
SampleFDO profile is updated. It is because some very large blocks with
a bunch of PHIs at the beginning. LiveDebugVariables::emitDebugValues
called during VirtRegRewriter phase searchs the insertion point for those
large BBs repeatedly in SkipPHIsLabelsAndDebug, and each time
SkipPHIsLabelsAndDebug needs to go through the same set of PHIs before it
can find the first non PHI/Label/Debug instruction. This patch adds a cache
to save the last position for the sequence which has been checked in the
previous call of SkipPHIsLabelsAndDebug.

Differential Revision: https://reviews.llvm.org/D94981
2021-01-28 21:58:17 -08:00
Max Kazantsev
6a837450cc [SCEV] Do not cache comparison result upon reached max depth as "equivalence". PR48725
We use `EquivalenceClasses` to cache the notion that two SCEVs are equivalent,
so save time in situation when `A` is equivalent to `B` and `B` is equivalent to `C`,
making check "if `A` is equivalent to `C`?" cheaper.

We also return `0` in the comparator when we reach max analysis depth to save
compile time. After doing this, we also cache them as being equivalent.

Now, imagine the following situation:
- `A` is proved equivalent to `B`;
- `C` is proved equivalent to `D`;
- Comparison of `A` against `D` is proved non-zero;
- Comparison of `B` against `C` reaches max depth (and gets cached as equivalence).

Now, before the invocation of compare(`B`, `C`), `A` and `D` belonged
to different equivalence classes, and their comparison returned non-zero.
After the the invocation of compare(`B`, `C`), equivalence classes get merged
and `A`, `B`, `C` and `D` all fall into the same equivalence class. So the comparator
will change its behavior for couple `A` and `D`, with weird consequences following it.
This comparator is finally used in `std::stable_sort`, and this behavior change
makes it crash (looks like it's causing a memory corruption).

Solution: this patch changes `CompareSCEVComplexity` to return `None`
when the max depth is reached. So in this case, we do not cache these SCEVs
(and their parents in the tree) as being equivalent.

Differential Revision: https://reviews.llvm.org/D94654
Reviewed By: lebedev.ri
2021-01-29 12:08:34 +07:00
Christudasan Devadasan
e86b7c773c Support a list of CostPerUse values
This patch allows targets to define multiple cost
values for each register so that the cost model
can be more flexible and better used during the
register allocation as per the target requirements.

For AMDGPU the VGPR allocation will be more efficient
if the register cost can be associated dynamically
based on the calling convention.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D86836
2021-01-29 10:14:52 +05:30
Yang Fan
c92db3d4c4 [NFC][DebugInfo] Fix Wreturn-type gcc warning
GCC warning:
```
/llvm-project/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp: In member function ‘llvm::Expected<long unsigned int> llvm::dwarf::CFIProgram::Instruction::getOperandAsUnsigned(const llvm::dwarf::CFIProgram&, uint32_t) const’:
/llvm-project/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp:425:1: warning: control reaches end of non-void function [-Wreturn-type]
  425 | }
      | ^
/llvm-project/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp: In member function ‘llvm::Expected<long int> llvm::dwarf::CFIProgram::Instruction::getOperandAsSigned(const llvm::dwarf::CFIProgram&, uint32_t) const’:
/llvm-project/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp:477:1: warning: control reaches end of non-void function [-Wreturn-type]
  477 | }
      | ^
```
2021-01-29 11:42:23 +08:00
Yang Fan
39bdc30ed4 [NFC][llvm-nm] Fix unused variable warning 2021-01-29 11:42:23 +08:00
Carl Ritson
bc3428f564 [AMDGPU] Fix WMM Entry SCC preservation
SCC was not correctly preserved when entering WWM.
Current lit test was unable to detect this as entry block is
handled differently.
Additionally fix an issue where SCC was unnecessarily preserved
when exiting from WWM to Exact mode.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D95500
2021-01-29 10:05:36 +09:00
Jessica Paquette
a395dfa5bd [GlobalISel] Implement regbankselect for G_ASSERT_ZEXT
This adds generic regbankselect support for G_ASSERT_ZEXT.

It inherits whatever register bank the source was given, always, on all targets.

I think that at the point where we run into these, the source register bank
should be decided.

This also adds some AArch64-specific code which makes sure we can handle
G_ASSERT_ZEXT when deciding on register banks for G_STORE, G_PHI, ... etc.

Differential Revision: https://reviews.llvm.org/D95649
2021-01-28 16:56:14 -08:00
Carl Ritson
88bf797971 [AMDGPU] Mark V_SET_INACTIVE as defining SCC
V_SET_INACTIVE is implemented with S_NOT which clobbers SCC.
Mark sure it is marked appropriately.

Reviewed By: piotr

Differential Revision: https://reviews.llvm.org/D95509
2021-01-29 09:46:41 +09:00
Amara Emerson
1a63466277 [AArch64][GlobalISel] Enable CSE for the prelegalizer combiner.
Differential Revision: https://reviews.llvm.org/D95647
2021-01-28 16:38:49 -08:00
Jessica Paquette
4ae121a0d4 [GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT
It's the same as the ZEXT/TRUNC case, except SrcBitWidth is given by the
immediate operand.

Update KnownBitsTest.cpp and a MIR test for a concrete example.

Differential Revision: https://reviews.llvm.org/D95566
2021-01-28 16:34:34 -08:00
Amara Emerson
0c8b3180a3 [AArch64][GlobalISel] Add a combine to fold away truncate in: G_ICMP EQ/NE (G_TRUNC(v), 0)
We try to do this optimization if we can determine that testing for the
truncated bits with an eq/ne predicate results in the same thing as testing
the lower bits.

Differential Revision: https://reviews.llvm.org/D95645
2021-01-28 16:29:14 -08:00
Greg Clayton
1948f133bc Fix windows buildbot build errors from D89845. 2021-01-28 15:25:10 -08:00