RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity
19,624 Commits 4 Branches 5 Tags 704 MiB
ac699c4db9
Commit Graph

10673 Commits

Author SHA1 Message Date
Chris Lattner
ac699c4db9 Print physreg register nodes with target names (e.g. F1) instead of numbers 
llvm-svn: 22934
 2005-08-19 21:21:16 +00:00
Chris Lattner
011a721d08 Before implementing copyfromreg, we'll implement copytoreg correctly. 
This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)

llvm-svn: 22933
 2005-08-19 20:50:53 +00:00
Chris Lattner
9af3aaf541 Now that we have operand info for machine instructions, use it to create 
temporary registers for things that define a register.  This allows dag->dag
isel to compile this:

int %test() { ret int 65535 }

into:

_test:
        lis r2, 0
        ori r2, r2, 65535
        blr

Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.

llvm-svn: 22932
 2005-08-19 20:45:43 +00:00
Chris Lattner
2ac3fd08d2 Split RegisterClass 'Methods' into MethodProtos and MethodBodies 
llvm-svn: 22929
 2005-08-19 19:13:20 +00:00
Chris Lattner
78107cb342 put reg classes into namespace 
llvm-svn: 22927
 2005-08-19 18:53:43 +00:00
Chris Lattner
2b1d327d29 Put reg classes into namespaces 
llvm-svn: 22926
 2005-08-19 18:52:55 +00:00
Chris Lattner
f86654ffde Put register classes into namespaces 
llvm-svn: 22925
 2005-08-19 18:51:57 +00:00
Chris Lattner
9d61d4a3e4 Put register classes in namespaces 
llvm-svn: 22924
 2005-08-19 18:50:46 +00:00
Chris Lattner
15d2e8a253 Fix code that assumes the register info will be dumped into a target 
namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.

llvm-svn: 22923
 2005-08-19 18:50:11 +00:00
Chris Lattner
47005fe346 put reg classes in namespaces 
llvm-svn: 22922
 2005-08-19 18:49:22 +00:00
Chris Lattner
9a9fe27bd2 Require that targets specify a namespace for their register classes. 
llvm-svn: 22921
 2005-08-19 18:48:48 +00:00
Chris Lattner
61526c0f6c The skeleton target has never had an isel 
llvm-svn: 22917
 2005-08-19 18:35:41 +00:00
Chris Lattner
f0b42a6f29 This code has always been dead on itanium 
llvm-svn: 22916
 2005-08-19 18:34:37 +00:00
Chris Lattner
b46e525e23 This code has always been dead for alpha 
llvm-svn: 22915
 2005-08-19 18:33:26 +00:00
Chris Lattner
e894de1791 The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Chris Lattner
f0e731ea49 Now that the simple isels are dead, so is this. 
llvm-svn: 22913
 2005-08-19 18:30:39 +00:00
Chris Lattner
db827889e3 Sparcv9 gets no operand info 
llvm-svn: 22909
 2005-08-19 16:56:56 +00:00
Jeff Cohen
12674110d5 Fix VC++ constant truncation warning. 
llvm-svn: 22907
 2005-08-19 16:19:21 +00:00
Duraid Madina
4efc0b6f2b a bugfix (up top) and a quick repair job: disable generation of dep.z 
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.

llvm-svn: 22904
 2005-08-19 13:25:50 +00:00
Jeff Cohen
f99748bc0f Fix VC++ precedence warning. 
llvm-svn: 22902
 2005-08-19 04:39:48 +00:00
Nate Begeman
88bfe8a7c3 Fix a bug where we were passing the wrong number of arguments to an 
instruction.

llvm-svn: 22901
 2005-08-19 03:42:28 +00:00
Chris Lattner
1207209677 Fix computation of # operands, add a temporary hack for CopyToReg 
llvm-svn: 22896
 2005-08-19 01:01:34 +00:00
Chris Lattner
5cfc567fb8 mark variable arity instructions as such. Alpha wins the battle for 
cleanest backend in this metric :)

llvm-svn: 22893
 2005-08-19 00:51:37 +00:00
Chris Lattner
5194ff37c4 Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(

llvm-svn: 22892
 2005-08-19 00:47:42 +00:00
Chris Lattner
d7bd59d77e add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman
1182e06dcf ISD::OR, and it's accompanying SelectBitfieldInsert 
llvm-svn: 22889
 2005-08-19 00:38:14 +00:00
Chris Lattner
abad70eaf8 The variable SAR's only take one operand too 
llvm-svn: 22888
 2005-08-19 00:31:37 +00:00
Chris Lattner
8ce7dd449a Stop adding bogus operands to variable shifts on X86. These instructions 
only take one operand.  The other comes implicitly in through CL.

llvm-svn: 22887
 2005-08-19 00:16:17 +00:00
Nate Begeman
a978ae8b7d Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.

llvm-svn: 22886
 2005-08-18 23:53:15 +00:00
Nate Begeman
c1aeaed2b9 Add shifts. 
llvm-svn: 22884
 2005-08-18 23:38:00 +00:00
Chris Lattner
1d3d2fb435 Fix operand numbers by marking variable arity nodes as such and by fixing 
the operand lists of a few other nodes.

llvm-svn: 22883
 2005-08-18 23:25:33 +00:00
Chris Lattner
9b342804a8 MFLR doesn't take an operand, the LR register is implicit 
llvm-svn: 22882
 2005-08-18 23:24:50 +00:00
Chris Lattner
32120e461e Add a new flag 
llvm-svn: 22881
 2005-08-18 23:17:07 +00:00
Chris Lattner
7b9f02525e add a new -view-sched-dags option to view dags as they are sent to the scheduler. 
llvm-svn: 22878
 2005-08-18 20:11:49 +00:00
Chris Lattner
2147daa960 Move this to the emitter 
llvm-svn: 22877
 2005-08-18 20:08:53 +00:00
Chris Lattner
62bc771af7 Implement the first chunk of a code emitter. This is sophisticated enough to 
codegen:

_empty:
.LBB_empty_0:   ;
        blr

but can't do anything more (yet). :)

llvm-svn: 22876
 2005-08-18 20:07:59 +00:00
Jim Laskey
7399a3d644 More optimal solution for loading constants. 
llvm-svn: 22870
 2005-08-18 18:58:23 +00:00
Chris Lattner
a094a1279a After selecting the instructions for a basic block, emit the instructions 
llvm-svn: 22869
 2005-08-18 18:46:06 +00:00
Chris Lattner
ebb48e5877 new file, obviously just a stub 
llvm-svn: 22868
 2005-08-18 18:45:24 +00:00
Chris Lattner
80a5ffb6c5 remove some unused stuff 
llvm-svn: 22866
 2005-08-18 18:34:00 +00:00
Nate Begeman
7efd8aa1d1 Fix int foo() { return 65535; } by using the top 16 bits of the constant 
as the argument to LIS rather than the result of HA16(constant).

The DAG->DAG ISel was already doing the right thing.

llvm-svn: 22865
 2005-08-18 18:14:49 +00:00
Nate Begeman
7726312fac Improve ISD::Constant codegen. 
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr

llvm-svn: 22864
 2005-08-18 18:01:39 +00:00
Chris Lattner
5cbeaed711 Enable critical edge splitting by default 
llvm-svn: 22863
 2005-08-18 17:35:14 +00:00
Chris Lattner
79b0fc3b9a replace switch stmt with an assert, generate li 0 instead of lis 0 for 0, 
to make the code follow people's expectations better.

llvm-svn: 22861
 2005-08-18 17:16:52 +00:00
Jim Laskey
ed406c683b Handle loading of 0x????0000 constants with a single instruction. 
llvm-svn: 22858
 2005-08-18 15:52:30 +00:00
Nate Begeman
67f3483a97 Add support for ISD::AND, and its various optimized forms. 
llvm-svn: 22857
 2005-08-18 07:30:46 +00:00
Nate Begeman
474ec3c02d Add support for target DAG nodes that take 4 operands, such as PowerPC's 
rlwinm.

llvm-svn: 22856
 2005-08-18 07:30:15 +00:00
Nate Begeman
3681359c93 Maintain consistency in negating things 
llvm-svn: 22855
 2005-08-18 05:44:50 +00:00
Nate Begeman
b6e36decb6 Implement XOR, remove a broken sign_extend_inreg case 
llvm-svn: 22854
 2005-08-18 05:00:13 +00:00