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Author SHA1 Message Date
Dan Gohman
ad77b290d0 Add some comments. 
llvm-svn: 104268
 2010-05-20 20:00:41 +00:00
Dan Gohman
b08c4f5ab9 Simplify this code. Don't do a DomTreeNode lookup for each visited block. 
llvm-svn: 104267
 2010-05-20 20:00:25 +00:00
Devang Patel
32a1ce3b3a Refactor. 
llvm-svn: 104265
 2010-05-20 19:57:06 +00:00
Matt Fleming
eb6f789e6f Grammar fix. This is a test commit. 
llvm-svn: 104264
 2010-05-20 19:45:09 +00:00
Dan Gohman
86f6190fc2 Minor code cleanups. 
llvm-svn: 104263
 2010-05-20 19:44:23 +00:00
Dan Gohman
89f64e13fe When canonicalizing icmp operand order to put the loop invariant 
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.

llvm-svn: 104262
 2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
ed1c9f41bf llvmc: Make segfault detection work on Win32. 
llvm-svn: 104261
 2010-05-20 19:23:47 +00:00
Dan Gohman
75ee6c3611 Set Changed to true when canonicalizing ICmp operand order; even though 
it isn't a very interesting change, it's a change nonetheless.

llvm-svn: 104260
 2010-05-20 19:16:03 +00:00
Bob Wilson
11aebf39f1 Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.

llvm-svn: 104257
 2010-05-20 18:39:53 +00:00
Jim Grosbach
5029c599b3 Remove dbg_value workaround and associated command line option 
llvm-svn: 104254
 2010-05-20 18:34:01 +00:00
Dan Gohman
7dcd59b8b2 Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't 
have a pattern and it had an invalid encoding.

llvm-svn: 104244
 2010-05-20 18:05:01 +00:00
Dale Johannesen
78714b5dc9 The PPC MFCR instruction implicitly uses all 8 of the CR 
registers.  Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
 vreg = MCRF  CR0
 MFCR  <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment).  That avoids all problems.  7739628.

llvm-svn: 104238
 2010-05-20 17:48:26 +00:00
Devang Patel
ae24244a10 Strip llvm.dbg.lv also. 
llvm-svn: 104236
 2010-05-20 16:49:22 +00:00
Dan Gohman
af66103d32 Rename a variable to avoid shadowing. 
llvm-svn: 104234
 2010-05-20 16:41:11 +00:00
Devang Patel
f90f78669f Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. 
llvm-svn: 104233
 2010-05-20 16:36:41 +00:00
Dan Gohman
db5be4dfc7 Minor code simplification. 
llvm-svn: 104232
 2010-05-20 16:23:28 +00:00
Dan Gohman
c8b4555a94 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00
Dan Gohman
80d2fc54e9 Set neverHasSideEffects on 64-bit pushf and popf, for consistency with 
16-bit and 32-bit pushf and popf.

llvm-svn: 104228
 2010-05-20 15:42:55 +00:00
Dan Gohman
139527105c Move the code for deleting BaseRegs and LSRUses into helper functions, 
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.

llvm-svn: 104225
 2010-05-20 15:17:54 +00:00
Benjamin Kramer
47bf53a5dd Reduce string trashing. 
llvm-svn: 104223
 2010-05-20 14:14:22 +00:00
Evan Cheng
0d88ad2de1 Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
 2010-05-20 06:13:19 +00:00
Nick Lewycky
8d3f839753 Fix typo in comment. 
llvm-svn: 104209
 2010-05-20 03:30:09 +00:00
Dan Gohman
52dcd5fb9a Define the x86 pause instruction. 
llvm-svn: 104204
 2010-05-20 01:35:50 +00:00
Dan Gohman
00b8752500 Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it 
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203
 2010-05-20 01:23:41 +00:00
Eric Christopher
09658d704d Fix build by actually declaring the variable. 
llvm-svn: 104201
 2010-05-20 00:59:30 +00:00
Eric Christopher
1a7bc06b28 Partial code for emitting thread local bss data. 
llvm-svn: 104197
 2010-05-20 00:49:07 +00:00
Bill Wendling
e7a42798bc Match "4" or "8" depending upon if it's 32- or 64-bit. 
llvm-svn: 104196
 2010-05-20 00:27:10 +00:00
Eric Christopher
1643e2f4c6 Once more, with feeling. 
llvm-svn: 104190
 2010-05-20 00:07:13 +00:00
Daniel Dunbar
1c27a3b79d lit: Add another place to look for bash. 
llvm-svn: 104189
 2010-05-19 23:56:09 +00:00
Dan Gohman
772b731ca5 Teach LSR how to cope better with unrolled loops on targets where 
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.

llvm-svn: 104186
 2010-05-19 23:43:12 +00:00
Bob Wilson
2dbe0d9886 Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185
 2010-05-19 23:42:58 +00:00
Chris Lattner
aedd148163 fix rdar://7986634 - match instruction opcodes case insensitively. 
llvm-svn: 104183
 2010-05-19 23:34:33 +00:00
Bill Wendling
483ce4b9b7 Testcase for r104181. 
llvm-svn: 104182
 2010-05-19 23:33:26 +00:00
Jim Grosbach
c991014a15 Enable preserving debug information through post-RA scheduling 
llvm-svn: 104175
 2010-05-19 22:57:47 +00:00
Jim Grosbach
523fa7acaa Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174
 2010-05-19 22:57:06 +00:00
Evan Cheng
9fe8c861bf Code clean up. 
llvm-svn: 104173
 2010-05-19 22:42:23 +00:00
Devang Patel
069568c287 Revert r104165. 
llvm-svn: 104172
 2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
f41b1697fe Add support for partial redefs to the fast register allocator. 
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

llvm-svn: 104167
 2010-05-19 21:36:05 +00:00
Devang Patel
d0b5830f72 There is no need to maintain InsnsBeginScopeSet separately. 
llvm-svn: 104165
 2010-05-19 21:26:53 +00:00
Eric Christopher
8c8d643a87 A more combo tls testcase. 
llvm-svn: 104163
 2010-05-19 21:19:42 +00:00
Jakob Stoklund Olesen
56998cc8aa Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
 2010-05-19 20:36:22 +00:00
Eric Christopher
6b51010080 Few more simple tls testcases. 
llvm-svn: 104148
 2010-05-19 20:35:15 +00:00
Evan Cheng
46e08acfa5 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
6a2bfde3c8 TwoAddressInstructionPass doesn't really know how to merge live intervals when 
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146
 2010-05-19 20:08:00 +00:00
Mikhail Glushenkov
e3e13b67e2 llvmc: report an error if a child process segfaults. 
llvm-svn: 104145
 2010-05-19 19:24:32 +00:00
Eric Christopher
fd72aa1040 Attempt to run this test on x86 only. 
llvm-svn: 104143
 2010-05-19 18:59:37 +00:00
Bob Wilson
e5f623ac22 Testcase to go with 104141. 
llvm-svn: 104142
 2010-05-19 18:58:37 +00:00
Bob Wilson
ae9655920b When expanding a vector_shuffle, the element type may not be legal and may 
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141
 2010-05-19 18:48:32 +00:00
Daniel Dunbar
bfb199781d MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode(). 
llvm-svn: 104122
 2010-05-19 17:20:58 +00:00
Daniel Dunbar
9646c49298 MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same 
prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120
 2010-05-19 15:26:43 +00:00