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7304 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
ae01dc5e74 createMipsDelaySlotFillerPass added to mips codegen runtime 
llvm-svn: 41154
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes
7bca87bebd Added Branch Analysis support 
Added InsertNoop support

llvm-svn: 41153
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes
c7eaab9c92 LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added

llvm-svn: 41152
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes
d97285f98a InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes
bc755b9969 A Pass to insert Nops on intructions with DelaySlot 
llvm-svn: 41150
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes
d67580757e Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00
Anton Korobeynikov
3094846993 Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed 
hard to catch bugs with retaddr lowering

llvm-svn: 41104
 2007-08-15 17:12:32 +00:00
Chris Lattner
9fd664292f add a note. 
llvm-svn: 41103
 2007-08-15 16:58:38 +00:00
Evan Cheng
eef13203e7 Fix a typo pointd out by Maarten ter Huurne. 
llvm-svn: 41059
 2007-08-13 23:27:11 +00:00
Dan Gohman
2390ff5060 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049
 2007-08-13 20:03:06 +00:00
Chris Lattner
7dfec1ee54 Fix PR1607 
llvm-svn: 41048
 2007-08-13 18:42:37 +00:00
Chris Lattner
fedbfd5f47 expand a note 
llvm-svn: 41021
 2007-08-11 18:19:07 +00:00
Chris Lattner
5f098dbbe5 With evan's explicit flag representation, hopefully we will finally be 
able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020
 2007-08-11 18:16:46 +00:00
Bill Wendling
e611c96a3c 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment. 
Make a 'memop' pattern just for them.

llvm-svn: 41017
 2007-08-11 09:52:53 +00:00
Christopher Lamb
7e52a97df5 Use subregs to improve any_extend code generation when feasible. 
llvm-svn: 41013
 2007-08-10 22:22:41 +00:00
Christopher Lamb
450f6815b9 Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
llvm-svn: 41010
 2007-08-10 21:48:46 +00:00
Christopher Lamb
4e6cae3eae Edit README in light of previous LEA16 commit. 
llvm-svn: 41009
 2007-08-10 21:29:05 +00:00
Christopher Lamb
7196f0d724 Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
llvm-svn: 41007
 2007-08-10 21:18:25 +00:00
Rafael Espindola
b20b9e985a propagate struct size and alignment of byval arguments to the DAG 
llvm-svn: 40986
 2007-08-10 14:44:42 +00:00
Bill Wendling
d0bee665d3 For kicks, I though it would be fun to use the correct opcode. 
llvm-svn: 40985
 2007-08-10 09:00:17 +00:00
Bill Wendling
55c3dc2409 Adding SSSE3 intrinsics. 
llvm-svn: 40982
 2007-08-10 06:22:27 +00:00
Evan Cheng
3fae8e1c4a Temporarily backing out this change until we know why some dejagnu tests are failing. 
llvm-svn: 40973
 2007-08-09 22:25:35 +00:00
Evan Cheng
a58ebc46dd divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
llvm-svn: 40972
 2007-08-09 21:59:35 +00:00
Evan Cheng
a822456bed GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
llvm-svn: 40970
 2007-08-09 18:05:17 +00:00
Dale Johannesen
79551baaad long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958
 2007-08-09 01:04:01 +00:00
Dale Johannesen
6c8f73eac6 Fix arguments for some Altivec instructions. From SWB. 
llvm-svn: 40957
 2007-08-09 00:49:19 +00:00
Dale Johannesen
0ea7df37c4 Fix spelling of mtvscr and mfvscr. 
llvm-svn: 40908
 2007-08-07 23:08:00 +00:00
Dale Johannesen
6b8e91e7e3 Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
 2007-08-07 20:29:26 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Dale Johannesen
2c35d56edd Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
 2007-08-07 01:17:37 +00:00
Dale Johannesen
92be0d49fb Replace 4-line function with 10-line version per review comment. 
llvm-svn: 40881
 2007-08-06 22:10:35 +00:00
Dale Johannesen
4df87d9305 Move lengthy conditional down 1 level per review comment. 
llvm-svn: 40878
 2007-08-06 21:48:35 +00:00
Dale Johannesen
3ea9879011 Get X86 long double calling convention to work 
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877
 2007-08-06 21:31:06 +00:00
Dale Johannesen
e3f1d06ca0 Make 80-bit store maintain simulated FP stack correctly. 
llvm-svn: 40868
 2007-08-06 19:50:32 +00:00
Reid Spencer
3e54e72ef1 Fix minor doxygen nits. 
llvm-svn: 40854
 2007-08-05 20:06:04 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.

llvm-svn: 40847
 2007-08-05 18:49:15 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
 2007-08-04 01:51:18 +00:00
Dale Johannesen
c8462173c5 Make x86 long double alignment 32 for everything but 
Darwin (which makes size within a struct==96)

llvm-svn: 40796
 2007-08-03 22:46:15 +00:00
Dale Johannesen
4b91728849 long double patch 2 of N. Handle it in TargetData. 
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792
 2007-08-03 20:20:50 +00:00
Chris Lattner
a9026e5f12 add an observation 
llvm-svn: 40772
 2007-08-03 00:17:42 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Dan Gohman
1afde4166e Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756
 2007-08-02 21:17:01 +00:00
Dan Gohman
7d1e35e6d1 Fix pastos in vector arithmetic intrinsics. 
llvm-svn: 40754
 2007-08-02 21:06:40 +00:00
Dan Gohman
a599a813d5 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736
 2007-08-02 14:27:55 +00:00
Evan Cheng
3163814591 Switch some multiplication instructions over to the new scheme for testing. 
llvm-svn: 40723
 2007-08-02 05:48:35 +00:00
Evan Cheng
019ecf3b91 Can't handle offset and scale if rip-relative addressing is to be used. 
llvm-svn: 40703
 2007-08-01 23:46:47 +00:00
Evan Cheng
69bbf3ed2a Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40702
 2007-08-01 23:46:10 +00:00
Evan Cheng
0fa6cdbff5 Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40701
 2007-08-01 23:45:51 +00:00
Evan Cheng
b050c17b31 Some out operands were incorrectly specified as input operands. 
llvm-svn: 40697
 2007-08-01 23:07:38 +00:00
Evan Cheng
defb3b8389 Missing Requires. 
llvm-svn: 40691
 2007-08-01 21:42:24 +00:00