RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity
19,626 Commits 4 Branches 5 Tags 704 MiB
b36807b0d0
Commit Graph

19626 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Chris Lattner
b36807b0d0 Fix a bug in previous commit 
llvm-svn: 22936
 2005-08-19 21:34:13 +00:00
Chris Lattner
a8f147c1b4 Fix a typeo, no wonder all tokenfactor edges were the same! 
llvm-svn: 22935
 2005-08-19 21:33:02 +00:00
Chris Lattner
ac699c4db9 Print physreg register nodes with target names (e.g. F1) instead of numbers 
llvm-svn: 22934
 2005-08-19 21:21:16 +00:00
Chris Lattner
011a721d08 Before implementing copyfromreg, we'll implement copytoreg correctly. 
This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)

llvm-svn: 22933
 2005-08-19 20:50:53 +00:00
Chris Lattner
9af3aaf541 Now that we have operand info for machine instructions, use it to create 
temporary registers for things that define a register.  This allows dag->dag
isel to compile this:

int %test() { ret int 65535 }

into:

_test:
        lis r2, 0
        ori r2, r2, 65535
        blr

Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.

llvm-svn: 22932
 2005-08-19 20:45:43 +00:00
Chris Lattner
9ceee53f9a Emit this: 
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931
 2005-08-19 20:29:14 +00:00
Chris Lattner
916e016ac1 Expose the derived register classes to the public header, allowing them 
to be accessed.

llvm-svn: 22930
 2005-08-19 20:23:42 +00:00
Chris Lattner
2ac3fd08d2 Split RegisterClass 'Methods' into MethodProtos and MethodBodies 
llvm-svn: 22929
 2005-08-19 19:13:20 +00:00
Chris Lattner
20c1c4cf07 Split register class "Methods" into MethodProtos and MethodBodies 
llvm-svn: 22928
 2005-08-19 19:12:51 +00:00
Chris Lattner
78107cb342 put reg classes into namespace 
llvm-svn: 22927
 2005-08-19 18:53:43 +00:00
Chris Lattner
2b1d327d29 Put reg classes into namespaces 
llvm-svn: 22926
 2005-08-19 18:52:55 +00:00
Chris Lattner
f86654ffde Put register classes into namespaces 
llvm-svn: 22925
 2005-08-19 18:51:57 +00:00
Chris Lattner
9d61d4a3e4 Put register classes in namespaces 
llvm-svn: 22924
 2005-08-19 18:50:46 +00:00
Chris Lattner
15d2e8a253 Fix code that assumes the register info will be dumped into a target 
namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.

llvm-svn: 22923
 2005-08-19 18:50:11 +00:00
Chris Lattner
47005fe346 put reg classes in namespaces 
llvm-svn: 22922
 2005-08-19 18:49:22 +00:00
Chris Lattner
9a9fe27bd2 Require that targets specify a namespace for their register classes. 
llvm-svn: 22921
 2005-08-19 18:48:48 +00:00
Chris Lattner
cef54bfd28 Refactor to use Target.getRegisterClasses consistently, which provides 
anonymous regclass definition renaming.

Change the generated code to emit register classes as properly namespace
qualified entities like everything else.

expose the actual class definition as an object, though this isn't quite
usable yet.

llvm-svn: 22920
 2005-08-19 18:47:59 +00:00
Chris Lattner
077a4e87c4 Emit real operand info for instructions. This currently works but is bad 
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919
 2005-08-19 18:46:26 +00:00
Chris Lattner
341308dc6b Read the namespace field from register classes 
llvm-svn: 22918
 2005-08-19 18:45:20 +00:00
Chris Lattner
61526c0f6c The skeleton target has never had an isel 
llvm-svn: 22917
 2005-08-19 18:35:41 +00:00
Chris Lattner
f0b42a6f29 This code has always been dead on itanium 
llvm-svn: 22916
 2005-08-19 18:34:37 +00:00
Chris Lattner
b46e525e23 This code has always been dead for alpha 
llvm-svn: 22915
 2005-08-19 18:33:26 +00:00
Chris Lattner
e894de1791 The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Chris Lattner
f0e731ea49 Now that the simple isels are dead, so is this. 
llvm-svn: 22913
 2005-08-19 18:30:39 +00:00
Chris Lattner
bf7633b73b add a setName method to record 
llvm-svn: 22912
 2005-08-19 17:58:49 +00:00
Chris Lattner
1344e9cf9c Add a setName method to Record. 
llvm-svn: 22911
 2005-08-19 17:58:11 +00:00
Chris Lattner
36f99a1374 For now, just emit empty operand info structures. 
llvm-svn: 22910
 2005-08-19 16:57:28 +00:00
Chris Lattner
db827889e3 Sparcv9 gets no operand info 
llvm-svn: 22909
 2005-08-19 16:56:56 +00:00
Chris Lattner
6fcfaee2fc Add a new field to TargetInstrDescriptor for tracking information about 
operands.

llvm-svn: 22908
 2005-08-19 16:56:26 +00:00
Jeff Cohen
12674110d5 Fix VC++ constant truncation warning. 
llvm-svn: 22907
 2005-08-19 16:19:21 +00:00
Jeff Cohen
c6e28f4d38 Update Visual Studio projects for removed file. 
llvm-svn: 22905
 2005-08-19 13:51:22 +00:00
Duraid Madina
4efc0b6f2b a bugfix (up top) and a quick repair job: disable generation of dep.z 
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.

llvm-svn: 22904
 2005-08-19 13:25:50 +00:00
Chris Lattner
5ac318c67b Fix a problem jeffc noticed 
llvm-svn: 22903
 2005-08-19 06:16:04 +00:00
Jeff Cohen
f99748bc0f Fix VC++ precedence warning. 
llvm-svn: 22902
 2005-08-19 04:39:48 +00:00
Nate Begeman
88bfe8a7c3 Fix a bug where we were passing the wrong number of arguments to an 
instruction.

llvm-svn: 22901
 2005-08-19 03:42:28 +00:00
Chris Lattner
95a4e948da remove dead args 
llvm-svn: 22900
 2005-08-19 01:17:18 +00:00
Chris Lattner
3ddfd4fb7e remove dead options 
llvm-svn: 22899
 2005-08-19 01:16:18 +00:00
Chris Lattner
d00cbf7aa6 remove dead flags 
llvm-svn: 22898
 2005-08-19 01:14:40 +00:00
Chris Lattner
1685432a06 The code emitter generator only supports targets with 32-bit instruction 
words.  There is no way for one of these targets to have a > 32-bit immediate!

llvm-svn: 22897
 2005-08-19 01:04:33 +00:00
Chris Lattner
1207209677 Fix computation of # operands, add a temporary hack for CopyToReg 
llvm-svn: 22896
 2005-08-19 01:01:34 +00:00
Chris Lattner
7ab998463c now that all of the targets are clean w.r.t. the number of operands for each 
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

llvm-svn: 22895
 2005-08-19 00:59:49 +00:00
Nate Begeman
0966f7d0b9 Add support for target nodes with more than 3 operands, required by ppc 
llvm-svn: 22894
 2005-08-19 00:56:28 +00:00
Chris Lattner
5cfc567fb8 mark variable arity instructions as such. Alpha wins the battle for 
cleanest backend in this metric :)

llvm-svn: 22893
 2005-08-19 00:51:37 +00:00
Chris Lattner
5194ff37c4 Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(

llvm-svn: 22892
 2005-08-19 00:47:42 +00:00
Chris Lattner
d7bd59d77e add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman
1182e06dcf ISD::OR, and it's accompanying SelectBitfieldInsert 
llvm-svn: 22889
 2005-08-19 00:38:14 +00:00
Chris Lattner
abad70eaf8 The variable SAR's only take one operand too 
llvm-svn: 22888
 2005-08-19 00:31:37 +00:00
Chris Lattner
8ce7dd449a Stop adding bogus operands to variable shifts on X86. These instructions 
only take one operand.  The other comes implicitly in through CL.

llvm-svn: 22887
 2005-08-19 00:16:17 +00:00
Nate Begeman
a978ae8b7d Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.

llvm-svn: 22886
 2005-08-18 23:53:15 +00:00