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b448d31a6b
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90 Commits

Author SHA1 Message Date
Daniel Dunbar
b448d31a6b Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. 
llvm-svn: 151630
 2012-02-28 15:36:07 +00:00
Jia Liu
bdcd314be3 remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Evan Cheng
d29a22e4b0 Some ARM implementaions, e.g. A-series, does return stack prediction. That is, 
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
 2012-02-28 06:42:03 +00:00
Akira Hatanaka
874523adc5 Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is 
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668
 2012-02-03 04:33:00 +00:00
Akira Hatanaka
8477374125 Rename WrapperPIC. It is now used for both pic and static. 
llvm-svn: 146232
 2011-12-09 01:53:17 +00:00
Akira Hatanaka
2204c910be Implement 64-bit support for thread local storage handling. 
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175
 2011-12-08 20:34:32 +00:00
Akira Hatanaka
11fea5de78 Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.

llvm-svn: 143989
 2011-11-07 18:59:49 +00:00
Akira Hatanaka
856f4e30b2 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Akira Hatanaka
3f89f9bc37 Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka
37493224a9 Define variable HasMips64 in MipsTargetLowering. 
llvm-svn: 140569
 2011-09-26 21:47:02 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Akira Hatanaka
60ccc76576 Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
llvm-svn: 137831
 2011-08-17 17:45:08 +00:00
Akira Hatanaka
0179c7fa68 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Eli Friedman
842ea169de Code generation for 'fence' instruction. 
llvm-svn: 136283
 2011-07-27 22:21:52 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Eric Christopher
82c3bcfb14 Remove getRegClassForInlineAsmConstraint for Mips. 
Part of rdar://9643582

llvm-svn: 134084
 2011-06-29 19:04:31 +00:00
Akira Hatanaka
1e08980a21 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Akira Hatanaka
4806508364 Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already 
been defined in MipsInstrFPU.td.

llvm-svn: 132076
 2011-05-25 20:08:05 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Akira Hatanaka
74d45b54f1 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka
6f900185ed Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka
025720d06f Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Akira Hatanaka
b26c89ee68 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes
52c64a2eb3 Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
99619e5bef Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes
6c5db0236a Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Bruno Cardoso Lopes
e11d870459 Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again 
llvm-svn: 121164
 2010-12-07 19:04:14 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Dan Gohman
c768525273 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786
 2010-07-07 15:54:55 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
5c8db5ab3f Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Bruno Cardoso Lopes
014f8fc7b1 Add suport for VASTART on Mips. 
llvm-svn: 95506
 2010-02-06 21:00:02 +00:00
Evan Cheng
9057fea7ef Revert 95130. 
llvm-svn: 95160
 2010-02-02 23:55:14 +00:00
Evan Cheng
48375fbf4f Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. 
llvm-svn: 95130
 2010-02-02 21:29:10 +00:00
Evan Cheng
237629e476 Eliminate target hook IsEligibleForTailCallOptimization. 
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626
 2010-01-27 00:07:07 +00:00
Evan Cheng
4e3bc5efb7 Add a second ValueType argument to isFPImmLegal. 
llvm-svn: 85361
 2009-10-28 01:43:28 +00:00
Evan Cheng
151726ad30 Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
llvm-svn: 85281
 2009-10-27 19:56:55 +00:00
Evan Cheng
7cb9c456e5 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. 
Not functionality change yet.

llvm-svn: 82273
 2009-09-18 21:02:19 +00:00
Sandeep Patel
9c4e094e2a Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. 
llvm-svn: 80773
 2009-09-02 08:44:58 +00:00
Chris Lattner
4cebf6ca28 reintroduce support for Mips "small" section handling. This is 
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900
 2009-08-13 06:28:06 +00:00