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Commit Graph

187029 Commits

Author SHA1 Message Date
Lang Hames
b52ac8615c [JITLink] Remove relocation unit tests.
These tests were written before llvm-jitlink supported regression testing of
relocation support. They are now redundant.
2019-10-30 13:16:37 -07:00
Lang Hames
b6f80a70ba [JITLink] Add missing include, explicitly qualify STLExtras functions.
This should fix the failures on some bots due to commit
b9d8e23b806ca605c368f924cca75bdd090834c6.
2019-10-30 13:06:15 -07:00
Evandro Menezes
7348b241c1 [clang][llvm] Obsolete Exynos M1 and M2 2019-10-30 15:02:59 -05:00
LLVM GN Syncbot
5d65b565d1 gn build: Merge b9d8e23b806 2019-10-30 19:36:47 +00:00
Lang Hames
b24faad0cf [JITLink] Add a utility for splitting blocks at a given index.
LinkGraph::splitBlock will split a block at a given index, returning a new
block covering the range [ 0, index ) and modifying the original block to
cover the range [ index, original-block-size ). Block addresses, content,
edges and symbols will be updated as necessary. This utility will be used
in upcoming improvements to JITLink's eh-frame support.
2019-10-30 12:35:49 -07:00
Daniel Sanders
001e8e94bf [globalisel][docs] Add a pass index 2019-10-30 12:06:22 -07:00
Simon Pilgrim
a27a032703 [X86][SSE] Regenerate vector-rem tests 2019-10-30 18:58:53 +00:00
Simon Pilgrim
c3dc5a676c [X86] Regenerate memmove vector width tests 2019-10-30 18:58:53 +00:00
Evandro Menezes
b69a3a9962 [AArch64] Remove overlapping scheduling definitions (NFC)
The scheduling definitions for ASIMD transpose and zipping overlapped with
others a few lines below.  Somehow, they didn't raise errors before.

There seem to be other overlapping definitions.  Somehow, they still don't
raise errors.

Differential revision: https://reviews.llvm.org/D68353
2019-10-30 13:57:27 -05:00
David Tenty
f997a683ad Revert "[NFC] Rename LLVM_NO_DEAD_STRIP"
This reverts commit 11c2a85db8849db1a5907e80d9966592248ef825.
2019-10-30 14:56:20 -04:00
Daniel Sanders
aea8b50910 [globalisel][docs] Fix a label that was renamed 2019-10-30 11:47:29 -07:00
jasonliu
c8388d7b51 [PowerPC][AIX] Adds support for writing the data section in object files
Adds support for generating the XCOFF data section in object files for global variables with initialization.

Merged aix-xcoff-common.ll into aix-xcoff-data.ll.

Changed variable name charr to chrarray in the test case to test if readobj works with 8-character names.

Authored by: xingxue

Reviewers: hubert.reinterptrtcast, sfertile, jasonliu, daltenty, Xiangling_L.

Reviewed by: hubert.reinterpretcast, sfertile, daltenty.

Subscribers: DiggerLin, Wuzish, nemanjai, hiraditya, MaskRay, jsji, shchenz, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67125
2019-10-30 18:44:35 +00:00
Jeremy Morse
dceb00e734 [DebugInfo][DAG] Distinguish different kinds of location indirection
From SelectionDAGs point of view, debug variable locations specified with
dbg.declare and dbg.addr are indirect -- they specify the address of
something. But calling conventions might mean that a Value is placed on
the stack somewhere, and this too is indirection. Previously this was
mixed up in the "IsIndirect" field of DBG_VALUE insts; this patch
separates them by encoding the indirection in a DIExpression.

If we have a dbg.declare or dbg.addr, then the expression produces an
address that then becomes a DWARF memory location. We can represent
this by putting a DW_OP_deref on the _end_ of the expression. If a Value
has been placed on the stack, then we need to put a DW_OP_deref on the
_start_ of the expression, to load the Value from the stack and have
the rest of the expression operate on it.

Differential Revision: https://reviews.llvm.org/D69028
2019-10-30 18:41:44 +00:00
Alina Sbirlea
dfa5798f2b [LegacyPassManager] Delete BasicBlockPass/Manager.
Summary:
Delete the BasicBlockPass and BasicBlockManager, all its dependencies and update documentation.
The BasicBlockManager was improperly tested and found to be potentially broken, and was deprecated as of rL373254.

In light of the switch to the new pass manager coming before the next release, this patch is a first cleanup of the LegacyPassManager.

Reviewers: chandlerc, echristo

Subscribers: mehdi_amini, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69121
2019-10-30 11:40:16 -07:00
Simon Pilgrim
8eea69e935 [X86] Add FIXME comment to merge more of computeZeroableShuffleElements and getTargetShuffleAndZeroables 2019-10-30 18:30:01 +00:00
Simon Pilgrim
9bf97591e3 [X86][SSE] combineX86ShuffleChain - use resolveZeroablesFromTargetShuffle helper. NFCI. 2019-10-30 18:30:01 +00:00
Sanjay Patel
b57dcc1d56 [MSP430] fix typo in test name; NFC 2019-10-30 14:15:25 -04:00
Sanjay Patel
80aa1df9bc [MSP430] adjust tests for Shift Amount Threshold; NFC
Baseline results for D69120.

Patch by: @joanlluch (Joan LLuch)
2019-10-30 14:12:58 -04:00
LLVM GN Syncbot
53ef52138f gn build: Merge 29dc0b17de6 2019-10-30 17:40:59 +00:00
Alexey Bataev
252d29f761 [SLP] Vectorize jumbled stores.
Summary:
Patch adds support for vectorization of the jumbled stores. The value
operands are vectorized and then shuffled in the right order before
store.

Reviewers: RKSimon, spatel, hfinkel, mkuper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43339
2019-10-30 13:33:52 -04:00
Kevin P. Neal
53df013eb6 [NFC] Move this set of STRICT_* cases to be next to the non-strict cases.
Requested by Cameron McInally in D69275.
2019-10-30 13:32:27 -04:00
Jay Foad
b4c888fa24 [AMDGPU] Simplify VCCZ bug handling
Summary:
VCCZBugHandledSet was used to make sure we don't apply the same
workaround more than once to a single cbranch instruction, but it's not
necessary because the workaround involves inserting an s_waitcnt
instruction, which is enough for subsequent iterations to detect that no
further workaround is necessary.

Also beef up the test case to check that the workaround was only applied
once. I have also manually verified that the test still passes even if I
hack the big do-while loop in runOnMachineFunction to run a minimum of
five iterations.

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69621
2019-10-30 17:09:07 +00:00
David Tellenbach
d6a4caef6e [NFC][MachineOutliner] Fix typo in comment 2019-10-30 16:28:11 +00:00
Ikhlas Ajbar
9b793e3434 Fix pattern error for S2_tstbit_i instruction
It used to generate S2_tstbit_i with constant -33 which resulted in an assert.
The reason is log2_32 was called with 64bit value 0.
2019-10-30 11:21:48 -05:00
Simon Pilgrim
d809bfbcad [SLPVectorizer] Use getAPInt() for comparison. NFCI.
Technically integers can assert on getZExtValue() if beyond i64 range, and a fuzzer usually find this.....
2019-10-30 16:16:55 +00:00
Nico Weber
0c9af5a142 gn build: (manually) merge 67474c60d34 2019-10-30 11:23:54 -04:00
Xiangling Liao
ef87472fc9 [AIX] Lowering CPI/JTI/BA to MIR
Enable lowering of constant pool index, jump table index, and bloack address to MIR on AIX.

Differential Revision: https://reviews.llvm.org/D69264
2019-10-30 11:21:37 -04:00
David Tellenbach
84d0e6b63a [AArch64][MachineOutliner] Return address signing for outlined functions
Summary:
During AArch64 frame lowering instructions to enable return address
signing are inserted into function if needed. Functions generated during
machine outlining don't run through target frame lowering and hence are
missing such instructions.

This patch introduces the following changes:

  1. If not all functions that potentially participate in function outlining
     agree on their return address signing scope and their return address
     signing key, outlining is disabled for these functions.
  2. If not all functions that potentially participate in function outlining
     agree on their support for v8.3A features, outlining is disabled for
     these functions.
  2. If all candidate functions agree on the signing scope, signing key and
     and their support for v8.3 features, the outlined function behaves as
     if it had the same scope and key attributes and as if it would provide
     the same v8.3A support as the original functions.

Reviewers: olista01, paquette, t.p.northover, ostannard

Reviewed By: ostannard

Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69097
2019-10-30 15:20:16 +00:00
Jay Foad
a785d0624f [SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.
Summary:
This is used on AMDGPU for rounding from v3f64 (which is illegal) to
v3f32 (which is legal).

Subscribers: jvesely, nhaehnle, tpr, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69339
2019-10-30 15:18:21 +00:00
Georgii Rymar
de7d2c4397 [ObjectYAML] - Redefine LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::Hex*) as LLVM_YAML_IS_FLOW_SEQUENCE_VECTOR.
I am using it in https://reviews.llvm.org/D69399.

This change changes how obj2yaml dumps arrays of `llvm::yaml::Hex8/llvm::yaml::Hex16/llvm::yaml::Hex32`
from:

```
PayloadBytes:
- 0x01
- 0x02
...
```

To

```
PayloadBytes:    [ 0x01, 0x02, ... ]
```

The latter way is shorter and looks better for arrays.

Differential revision: https://reviews.llvm.org/D69558
2019-10-30 18:12:48 +03:00
Florian Hahn
a69a09c04c [bugpoint] Reduce metadata that does not contribute to crash.
Add a new reducer that drops metadata that does not contribute to the
crash from instructions.

It adjusts the metadata.ll test case, as now also the instruction level
metadata will get dropped.

Reviewers: davide, reames, modocache

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D69234
2019-10-30 15:11:56 +00:00
Roman Lebedev
abedf7e347 [NFC][LoopUnroll] Tests for peeling of first iteration (PR43840) 2019-10-30 18:08:54 +03:00
Jay Foad
9a5af2ea92 [IR] Allow fast math flags on calls with floating point array type.
Summary:
This extends the rules for when a call instruction is deemed to be an
FPMathOperator, which is based on the type of the call (i.e. the return
type of the function being called). Previously we only allowed
floating-point and vector-of-floating-point types. Now we also allow
arrays (nested to any depth) of floating-point and
vector-of-floating-point types.

This was motivated by llpc, the pipeline compiler for AMD GPUs
(https://github.com/GPUOpen-Drivers/llpc). llpc has many math library
functions that operate on vectors, typically represented as <4 x float>,
and some that operate on matrices, typically represented as
[4 x <4 x float>], and it's useful to be able to decorate calls to all
of them with fast math flags.

Reviewers: spatel, wristow, arsenm, hfinkel, aemerson, efriedma, cameron.mcinally, mcberg2017, jmolloy

Subscribers: wdng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69161
2019-10-30 14:00:33 +00:00
Krzysztof Parzyszek
55591bd837 LiveIntervals: Split live intervals on multiple dead defs
This is a follow-up to D67448.

Split live intervals with multiple dead defs during the initial
execution of the live interval analysis, but do it outside of the
function createAndComputeVirtRegInterval.

Differential Revision: https://reviews.llvm.org/D68666
2019-10-30 08:50:46 -05:00
Pavel Labath
23ce0d840e minidump: Rename some architecture constants
The architecture enum contains two kinds of contstants: the "official" ones
defined by Microsoft, and unofficial constants added by breakpad to cover the
architectures not described by the first ones.

Up until now, there was no big need to differentiate between the two. However,
now that Microsoft has defined
https://docs.microsoft.com/en-us/windows/win32/api/sysinfoapi/ns-sysinfoapi-system_info
a constant for ARM64, we have a name clash.

This patch renames all breakpad-defined constants with to include the prefix
"BP_". This frees up the name "ARM64", which I'll re-introduce with the new
"official" value in a follow-up patch.

Reviewers: amccarth, clayborg

Subscribers: lldb-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D69285
2019-10-30 14:46:00 +01:00
Djordje Todorovic
20040d1f56 [ARM][AArch64][DebugInfo] Improve call site instruction interpretation
Extend the describeLoadedValue() with support for target specific ARM and
AArch64 instructions interpretation. The patch provides specialization for
ADD and SUB operations that include a register and an immediate/offset
operand. Some of the instructions can operate with global string addresses
or constant pool indexes but such cases are omitted since we currently lack
flexible support for processing such operands at DWARF production stage.

Patch by Nikola Prica

Differential Revision: https://reviews.llvm.org/D67556
2019-10-30 13:58:14 +01:00
Kerry McLaughlin
14ec954f3c [AArch64][SVE] Implement masked store intrinsics
Summary:
Adds support for codegen of masked stores, with non-truncating
and truncating variants.

Reviewers: huntergr, greened, dmgreen, rovka, sdesmalen

Reviewed By: dmgreen, sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69378
2019-10-30 11:56:54 +00:00
Simon Pilgrim
483e0f37d7 [X86] combineOrShiftToFunnelShift - use isOperationLegalOrCustom to check FSHL/FSHR support
Remove hard wired legality check.
2019-10-30 11:52:22 +00:00
Simon Pilgrim
4786f7a0f6 [X86] combineOrShiftToFunnelShift - use getShiftAmountTy instead of hardwiring to MVT::i8 2019-10-30 11:52:22 +00:00
Kerry McLaughlin
e8f6c64289 [AArch64][SVE] Implement additional integer arithmetic intrinsics
Summary:
Add intrinsics for the following:
  - sxt[b|h|w] & uxt[b|h|w]
  - cls & clz
  - not & cnot

Reviewers: huntergr, sdesmalen, dancgr

Reviewed By: sdesmalen

Subscribers: cameron.mcinally, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69567
2019-10-30 11:31:54 +00:00
Jay Foad
b6fc016e4b [AMDGPU] Consolidate one more getGeneration check
This one should have been done in r363902 when hasReadVCCZBug was
introduced.
2019-10-30 11:16:42 +00:00
LLVM GN Syncbot
a11648a1fe gn build: Merge 6bf55804924 2019-10-30 10:43:37 +00:00
Georgii Rymar
29cf2215d1 [llvm-objcopy] - Do not crash on object that has relocations but no symbol table.
It was revealed by D69260.

Tool crashed when scanned relocations in a object without a symbol table.
This patch teaches it either to handle such objects (when relocations
does not use symbols we do not need a symbol table to proceed)
or to show an appropriate error otherwise.

Differential revision: https://reviews.llvm.org/D69304
2019-10-30 13:17:22 +03:00
Alex Richardson
bc49add214 [UpdateTestChecks] Fix invalid python string escapes 2019-10-30 09:36:20 +00:00
Guillaume Chatelet
c42952cec8 [Alignment] Use Align for TFI.getStackAlignment() in X86ISelLowering
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, craig.topper, rnk

Reviewed By: rnk

Subscribers: rnk, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69034
2019-10-30 10:35:13 +01:00
Alex Richardson
4c2f38b670 [update_cc_test_checks.py] Fix invalid python string escape sequence
This works with current python version but will be an error with 3.9
2019-10-30 09:28:51 +00:00
Karl-Johan Karlsson
d179aa00b3 [AddressSanitizer] Only instrument globals of default address space
The address sanitizer ignore memory accesses from different address
spaces, however when instrumenting globals the check for different
address spaces is missing. This result in assertion failure. The fault
was found in an out of tree target.

The patch skip all globals of non default address space.

Reviewed By: leonardchan, vitalybuka

Differential Revision: https://reviews.llvm.org/D68790
2019-10-30 09:32:19 +01:00
QingShan Zhang
6f49436f61 [PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern
If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well.
If not, the tblgen will set it as true that hurt the scheduling.

PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according
to the register pressure. We need to clear the sideeffect flag for these instructions.

Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 07:59:32 +00:00
Craig Topper
0ad4d87942 [Target] Change PATCHABLE_EVENT_CALL/PATCHABLE_TYPED_EVENT_CALL to use unknown instead of i8imm/i16imm/i32imm in its definition.
These instructions don't use immediates, they use registers. But
the register class needed is target specific. So just use unknown.
2019-10-30 00:36:01 -07:00
Craig Topper
f04a9f7eb5 [X86] Add test case for PR43758. NFC 2019-10-30 00:36:01 -07:00