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468 Commits

Author SHA1 Message Date
Chris Lattner
7592fe2d86 invert the sense of this switch and its name 
llvm-svn: 25234
 2006-01-12 01:28:56 +00:00
Nate Begeman
cff96008ac Add bswap, rotl, and rotr nodes 
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222
 2006-01-11 21:21:00 +00:00
Chris Lattner
8dd97ae338 This is no longer needed 
llvm-svn: 25219
 2006-01-11 19:52:46 +00:00
Chris Lattner
1ffbbc9ebc Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a 
pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.

llvm-svn: 25212
 2006-01-11 07:49:38 +00:00
Chris Lattner
c2bd047226 Fix a bug in i32->f64 conversion lowering 
llvm-svn: 25211
 2006-01-11 07:27:40 +00:00
Chris Lattner
34c4cddb14 Unbreak ret void :-/ 
llvm-svn: 25210
 2006-01-11 07:15:43 +00:00
Chris Lattner
d9b3f6a3df Write this pattern in canonical form, allowing more patterns to match. 
This implements Regression/CodeGen/SparcV8/xnor.ll

llvm-svn: 25209
 2006-01-11 07:14:01 +00:00
Evan Cheng
e720cfd690 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.

llvm-svn: 25155
 2006-01-09 18:28:21 +00:00
Chris Lattner
88239024ca silence a bogus gcc warning 
llvm-svn: 25129
 2006-01-06 17:56:38 +00:00
Jim Laskey
41b3ee3c4f Had expand logic backward. 
llvm-svn: 25105
 2006-01-05 01:47:43 +00:00
Jim Laskey
5eddaee9f3 Added initial support for DEBUG_LABEL allowing debug specific labels to be 
inserted in the code.

llvm-svn: 25104
 2006-01-05 01:25:28 +00:00
Evan Cheng
0d39dd2664 Remove some dead code. 
llvm-svn: 25102
 2006-01-05 00:26:14 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng
d87688fe72 * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Chris Lattner
738cec7a6e not a good idea 
llvm-svn: 24991
 2005-12-23 07:37:47 +00:00
Chris Lattner
2e386f9d46 fix something-o 
llvm-svn: 24987
 2005-12-23 07:08:39 +00:00
Chris Lattner
a4a2d4c3fe implement vaarg. Varargs now should work. 
llvm-svn: 24986
 2005-12-23 06:37:38 +00:00
Chris Lattner
4e8124bd9b implement vastart. The dag isel compiles this: 
void test3(va_list Y);
void test2(int F, ...) {
  va_list X;
  va_start(X, F);
  test3(X);
}

into this:

test2:
        save -104, %o6, %o6
        st %i5, [%i6+88]
        st %i4, [%i6+84]
        st %i3, [%i6+80]
        st %i2, [%i6+76]
        st %i1, [%i6+72]
        add %i6, 72, %o0
        st %o0, [%i6+-4]
        call test3
        nop
        restore %g0, %g0, %g0
        retl
        nop

The simple isel emits:

test2:
        save -96, %o6, %o6
        st %i0, [%i6+68]
        st %i1, [%i6+72]
        st %i2, [%i6+76]
        st %i3, [%i6+80]
        st %i4, [%i6+84]
        st %i5, [%i6+88]
        or %g0, 1, %l0
        or %g0, 4, %l1
        umul %l0, %l1, %l0
        add %l0, 7, %l0
        and %l0, -8, %l0
        sub %o6, %l0, %o6
        add %o6, 96, %l0
        add %i6, 72, %l1
        st %l1, [%l0]
        ld [%l0], %o0
        call test3
        nop
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24985
 2005-12-23 06:24:04 +00:00
Chris Lattner
73db2dc9fc remove benchmark list, remove issues addressed by the dag-dag isel 
llvm-svn: 24984
 2005-12-23 06:09:30 +00:00
Chris Lattner
8b2bd265f4 make sure bit_converts are expanded 
llvm-svn: 24978
 2005-12-23 05:13:35 +00:00
Chris Lattner
e47f28d044 fix the int<->fp instructions, which apparently take a single float register 
to represent the int part (because it's always 32-bits)

llvm-svn: 24976
 2005-12-23 05:00:16 +00:00
Chris Lattner
aaeb6774c7 Use BIT_CONVERT to simplify this code 
llvm-svn: 24975
 2005-12-23 02:31:39 +00:00
Chris Lattner
1cbff1f3cd clean up .td file by using evan's new FLAG thing 
llvm-svn: 24967
 2005-12-22 21:18:39 +00:00
Jim Laskey
d82881490c Disengage DEBUG_LOC from non-PPC targets. 
llvm-svn: 24919
 2005-12-21 20:51:37 +00:00
Chris Lattner
39b72c3525 remove dead code 
llvm-svn: 24896
 2005-12-21 05:27:51 +00:00
Chris Lattner
338c0b2011 Run lower-switch after lower-invoke. 
Only run lower-allocations and lower-select for the simple isel

llvm-svn: 24881
 2005-12-20 08:00:11 +00:00
Chris Lattner
ec177e242d Reserve G1 for frame offset stuff and use it to handle large stack frames. 
For example, instead of emitting this:

test:
        save -40112, %o6, %o6   ;; imm too large
        add %i6, -40016, %o0    ;; imm too large
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

emit this:

test:
        sethi 4194264, %g1
        or %g1, 848, %g1
        save %o6, %g1, %o6
        sethi 4194264, %g1
        add %g1, %i6, %g1
        add %i1, 944, %o0
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

which doesn't cause the assembler to barf.

llvm-svn: 24880
 2005-12-20 07:56:31 +00:00
Chris Lattner
7a430ddf61 Fix pifft by correcting the case when a i64/f64 straddles O5 and memory: 
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.

llvm-svn: 24859
 2005-12-19 07:57:53 +00:00
Chris Lattner
3d1946c765 don't emit 'add %o6, 0, %o6' instructions 
llvm-svn: 24857
 2005-12-19 02:51:12 +00:00
Chris Lattner
2aeb7fcbb3 Fix calls to functions returning i64 
llvm-svn: 24856
 2005-12-19 02:15:51 +00:00
Chris Lattner
63761db672 Correct bool truncstore operand order 
llvm-svn: 24855
 2005-12-19 02:06:50 +00:00
Chris Lattner
4fef952e4d add the other bool zextload as well 
llvm-svn: 24854
 2005-12-19 01:44:58 +00:00
Chris Lattner
91caf35bf5 implement zextload bool 
llvm-svn: 24853
 2005-12-19 01:43:04 +00:00
Chris Lattner
59f1a92c77 mark some unsupported ops as unsupported 
llvm-svn: 24852
 2005-12-19 01:39:40 +00:00
Chris Lattner
480e2f7945 Fix syntax for indirect calls. This fixes Olden/mst 
llvm-svn: 24850
 2005-12-19 01:22:53 +00:00
Chris Lattner
bd8b911c46 Keep stack frames 8-byte aligned. This fixes olden/voronoi 
llvm-svn: 24849
 2005-12-19 01:15:13 +00:00
Chris Lattner
b10b543e85 apparently rdy isn't actually a psuedo instruction. Use rd %y 
llvm-svn: 24848
 2005-12-19 00:53:02 +00:00
Chris Lattner
9e50ecd0d2 add fneg/fabs support for doubles 
llvm-svn: 24847
 2005-12-19 00:50:12 +00:00
Chris Lattner
0a579fb2ac Various cleanups to this pass, no functionality change 
llvm-svn: 24846
 2005-12-19 00:46:20 +00:00
Chris Lattner
be1adf763b add bool truncstores 
llvm-svn: 24845
 2005-12-19 00:19:21 +00:00
Chris Lattner
be3df4a199 Elimiante SP and FP, which weren't members of the IntRegs register class 
llvm-svn: 24844
 2005-12-19 00:06:52 +00:00
Chris Lattner
fdc05d74a6 The sun assembler only supports .xword in V9 mode. 
llvm-svn: 24842
 2005-12-18 23:36:45 +00:00
Chris Lattner
d0e25175d3 Configure the asmwriter to allow constant pools to be printed correctly 
llvm-svn: 24841
 2005-12-18 23:35:05 +00:00
Chris Lattner
84a2caf581 add support for integer extloads 
llvm-svn: 24840
 2005-12-18 23:18:37 +00:00
Chris Lattner
061cfe15c9 Add support for undef 
llvm-svn: 24839
 2005-12-18 23:10:57 +00:00
Chris Lattner
e8dad0dcb9 Add support for calls to external symbols 
llvm-svn: 24838
 2005-12-18 23:07:11 +00:00
Chris Lattner
745c88ba10 we have no memcpy 
llvm-svn: 24837
 2005-12-18 23:00:27 +00:00
Chris Lattner
d8c98dcfe0 Fix a crash on a call with no arguments 
llvm-svn: 24836
 2005-12-18 22:57:47 +00:00
Chris Lattner
27357a915a Change return lowering so that we can autogen the matching code. 
llvm-svn: 24832
 2005-12-18 21:03:04 +00:00
Chris Lattner
41ec63f309 Implement Calls for V8. This would be completely autogenerated except for 
a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.

llvm-svn: 24830
 2005-12-18 15:55:15 +00:00
Chris Lattner
b82f4641c4 Implement the full V8 ABI for incoming arguments. 
llvm-svn: 24825
 2005-12-18 13:33:06 +00:00
Chris Lattner
21ae63ceb9 Push ops list, asm string, and pattern all the way up to InstV8. Move the 
InstV8 class to the InstrFormats file where it belongs.

llvm-svn: 24824
 2005-12-18 08:21:00 +00:00
Chris Lattner
11fa3cc8ee Give V8 select_cc, in the spirit of the PPC backend 
llvm-svn: 24823
 2005-12-18 08:13:54 +00:00
Chris Lattner
6d46ed50a0 remove some unused instructions 
llvm-svn: 24822
 2005-12-18 07:15:17 +00:00
Chris Lattner
e0ebaa24f9 V8 doesn't have FP extload 
llvm-svn: 24821
 2005-12-18 07:13:32 +00:00
Chris Lattner
0d0850d22e simplifications, fix typo 
llvm-svn: 24820
 2005-12-18 07:09:06 +00:00
Chris Lattner
941ba22d08 Add frameindex support 
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions

llvm-svn: 24818
 2005-12-18 06:59:57 +00:00
Chris Lattner
7b7ea7c7bd Tighten up some checks 
llvm-svn: 24817
 2005-12-18 06:40:34 +00:00
Chris Lattner
2aab8f4471 Add constant pool support, including folding into addresses. 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]

llvm-svn: 24813
 2005-12-18 02:37:35 +00:00
Chris Lattner
cba8a96bd0 Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes, 
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24812
 2005-12-18 02:27:00 +00:00
Chris Lattner
5303e59b7a Add initial support for global variables, and fix a bug in addr mode selection 
where we didn't select the operands.

llvm-svn: 24811
 2005-12-18 02:10:39 +00:00
Chris Lattner
1294e27969 Claiming that branch targets are registers is not very wholesome. Change them 
to be basic blocks.  Also, add uncond branches.

llvm-svn: 24810
 2005-12-18 01:46:58 +00:00
Chris Lattner
f3a888d1dd Add unordered comparisons 
llvm-svn: 24809
 2005-12-18 01:41:39 +00:00
Chris Lattner
66e29f7ead Add patterns to the rest of the int condbranches and some of the fp branches 
llvm-svn: 24808
 2005-12-18 01:38:19 +00:00
Chris Lattner
47785d8fc3 Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.

llvm-svn: 24807
 2005-12-18 01:20:35 +00:00
Chris Lattner
9f0ac41d5c Eliminate CMPri, which is a synonym for SUBCCri 
llvm-svn: 24805
 2005-12-17 23:52:08 +00:00
Chris Lattner
95e9327303 add fneg,fabs,fsqrt instructions 
llvm-svn: 24803
 2005-12-17 23:20:27 +00:00
Chris Lattner
a9adf79113 Add patterns for fround/fextend and the funny fsmuld instruction 
llvm-svn: 24802
 2005-12-17 23:14:30 +00:00
Chris Lattner
ac03e1e55e Add FP +,-,*,/ 
llvm-svn: 24801
 2005-12-17 23:10:46 +00:00
Chris Lattner
13253a829a Give patterns to F3_3 instructions 
llvm-svn: 24800
 2005-12-17 23:05:35 +00:00
Chris Lattner
057fbaea0d Implement 64-bit add/sub, make sure to receive and return 64-bit args with 
the right halves in the right regs

llvm-svn: 24799
 2005-12-17 22:55:57 +00:00
Chris Lattner
a4865938dc implement div and rem 
llvm-svn: 24798
 2005-12-17 22:39:19 +00:00
Chris Lattner
88a3754b46 implement MULHU/MULHS for 64-bit multiplies 
llvm-svn: 24797
 2005-12-17 22:30:00 +00:00
Chris Lattner
7f9e66063d Add patterns for multiply, simplify Y register handling stuff, add RDY instruction 
llvm-svn: 24796
 2005-12-17 22:22:53 +00:00
Chris Lattner
a4dbacd0d6 Make the addressing modes smarter 
llvm-svn: 24795
 2005-12-17 21:25:27 +00:00
Chris Lattner
9bd197adae remove some unused instructions 
llvm-svn: 24794
 2005-12-17 21:13:50 +00:00
Chris Lattner
a17cbf352e add andn/orn/xorn patterns. This allows us to compile this: 
long %test(ubyte, short, long %X, long %Y) {
  %A = xor long %X, -1
  %B = and long %Y, %A
  ret long %B
}

to this:

test:
        save -96, %sp, %sp
        andn %i4, %i2, %i0
        andn %i5, %i3, %i1
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        xor %i2, -1, %l0
        xor %i3, -1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

The simpleisel emits:  :(

test:
        save -96, %sp, %sp
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l1
        xor %i2, %l0, %l0
        xor %i3, %l1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24793
 2005-12-17 21:05:49 +00:00
Chris Lattner
3afda7194f Add support for 64-bit arguments 
llvm-svn: 24792
 2005-12-17 20:59:06 +00:00
Chris Lattner
c1ab8a5e42 Sparc doesn't have sext_inreg 
llvm-svn: 24791
 2005-12-17 20:50:42 +00:00
Chris Lattner
a57b8986ea add patterns for FP stores 
llvm-svn: 24790
 2005-12-17 20:47:16 +00:00
Chris Lattner
abb86e4e22 Add [reg+reg] integer stores 
llvm-svn: 24789
 2005-12-17 20:44:36 +00:00
Chris Lattner
f9bc70e0ef Add store patterns 
llvm-svn: 24788
 2005-12-17 20:42:55 +00:00
Chris Lattner
bdfee98ec0 add fp load patterns, switch rest of loads and stores to use addrmodes 
llvm-svn: 24786
 2005-12-17 20:32:47 +00:00
Chris Lattner
d775f1de68 Add integer load[r+r] forms. 
llvm-svn: 24785
 2005-12-17 20:26:45 +00:00
Chris Lattner
d09afb735d Rename load/store instructions to include an RI suffix 
llvm-svn: 24784
 2005-12-17 20:18:49 +00:00
Chris Lattner
9133c2c38b Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts 
llvm-svn: 24783
 2005-12-17 20:18:24 +00:00
Chris Lattner
3e51b620ec Add basic addressing mode support and one load. 
llvm-svn: 24782
 2005-12-17 20:04:49 +00:00
Chris Lattner
e441738cef Use a combination of sethi and or to build arbitrary immediates. 
llvm-svn: 24780
 2005-12-17 19:41:43 +00:00
Chris Lattner
39740d3207 Use sethi to build large immediates with zeros at the bottom 
llvm-svn: 24779
 2005-12-17 19:37:00 +00:00
Chris Lattner
5893b95caa Add shift and small immediate support 
llvm-svn: 24778
 2005-12-17 19:07:57 +00:00
Chris Lattner
81b13ccb01 Add some basic reg-reg instructions 
llvm-svn: 24777
 2005-12-17 18:53:33 +00:00
Chris Lattner
058fe7d1ed Add empty patterns to all F3_1 instructions 
llvm-svn: 24776
 2005-12-17 18:49:14 +00:00
Chris Lattner
2ba4a8584c Add some simple integer patterns. This allows us to compile this: 
int %test(int %A) {
  %B = add int %A, 1
  %C = xor int %B, 123
  ret int %C
}

into this:

test:
        save -96, %sp, %sp
        add %i0, 1, %l0
        xor %l0, 123, %i0
        restore %g0, %g0, %g0
        retl
        nop

for example.  I guess it would make sense to add reg/reg versions too.

llvm-svn: 24774
 2005-12-17 08:26:38 +00:00
Chris Lattner
4de7491c52 Implement ret with operand, giving us this: 
int %test(int %A) {
  ret int %A
}

llvm-svn: 24773
 2005-12-17 08:15:09 +00:00
Chris Lattner
b877ae7929 Add a pattern for 'ret'. This now compiles: 
void %test() { ret void }

:)

llvm-svn: 24772
 2005-12-17 08:08:42 +00:00
Chris Lattner
e7408707fd Add empty patterns for F3_2 instructions 
llvm-svn: 24771
 2005-12-17 08:06:43 +00:00
Chris Lattner
3fca9488d2 Implement LowerArguments, at least for the first 6 integer args 
llvm-svn: 24770
 2005-12-17 08:03:24 +00:00
Chris Lattner
62aadddb9d Add the framework for a dag-dag isel 
llvm-svn: 24769
 2005-12-17 07:47:01 +00:00
Chris Lattner
adf84860db asmprinter done, added crucial missing step 
llvm-svn: 24767
 2005-12-17 07:17:59 +00:00
Chris Lattner
91e36127ed Use the AsmPrinter for global variable init printing. This eliminates a 
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.

llvm-svn: 24766
 2005-12-17 07:17:08 +00:00