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12003 Commits

Author SHA1 Message Date
Stuart Hastings
eb78f8db98 Support for nested functions/classes in debug output. Radar 7424645. 
llvm-svn: 105492
 2010-06-04 22:36:03 +00:00
Jakob Stoklund Olesen
f0226fee37 Slightly change the meaning of the reMaterialize target hook when the original 
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

llvm-svn: 105358
 2010-06-02 22:47:25 +00:00
Rafael Espindola
f7170870cf Remove the TargetRegisterClass member from CalleeSavedInfo 
llvm-svn: 105344
 2010-06-02 20:02:30 +00:00
Bob Wilson
fd208cef5d Rename canCombinedSubRegIndex method to something more grammatically correct 
and tidy up the comment describing it.

llvm-svn: 105339
 2010-06-02 18:54:47 +00:00
Jim Grosbach
90ca622864 remove trailing whitespace 
llvm-svn: 105333
 2010-06-02 17:45:54 +00:00
Rafael Espindola
7b9d713f40 Remove uses of getCalleeSavedRegClasses from outside the 
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.

llvm-svn: 105321
 2010-06-02 12:39:06 +00:00
Dan Gohman
940f8f3947 Don't call flush() at a library level which isn't checking for errors 
and doesn't know where the output is going.

llvm-svn: 105274
 2010-06-01 16:31:34 +00:00
Dan Gohman
196387f66e Fix a typo in a comment. 
llvm-svn: 105272
 2010-06-01 16:10:08 +00:00
Dan Gohman
ed310b8bca SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue 
shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.

llvm-svn: 105101
 2010-05-29 17:03:36 +00:00
Nick Lewycky
c80024c896 Fix typo. 
llvm-svn: 105096
 2010-05-29 06:11:16 +00:00
Dan Gohman
85f0f45ea1 Split the logic behind CastInst::isNoopCast into a separate static function, 
as is done with most other cast opcode predicates.

llvm-svn: 105008
 2010-05-28 21:41:37 +00:00
Dan Gohman
9de9456806 Fix a comment; vectors are not a special case here. 
llvm-svn: 105006
 2010-05-28 21:22:45 +00:00
Jakob Stoklund Olesen
6a3738d96a Add a TargetRegisterInfo::composeSubRegIndices hook with a default 
implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985
 2010-05-28 18:18:53 +00:00
Dan Gohman
0d7d3faf8e Move FindAvailableLoadedValue isSafeToLoadUnconditionally out of 
lib/Transforms/Utils and into lib/Analysis so that Analysis passes
can use them.

llvm-svn: 104949
 2010-05-28 16:19:17 +00:00
Dan Gohman
f7bbeb021a Fix a comment. 
llvm-svn: 104947
 2010-05-28 16:06:09 +00:00
Jakob Stoklund Olesen
d76041cf58 Add a -regalloc=default option that chooses a register allocator based on the -O 
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

llvm-svn: 104904
 2010-05-27 23:57:25 +00:00
Jakob Stoklund Olesen
9f9fed5a7c Remove ancient prototype. 
llvm-svn: 104903
 2010-05-27 23:57:19 +00:00
Jim Grosbach
d788f9b580 back out 104862/104869. Can reuse stacksave after all. Very cool. 
llvm-svn: 104897
 2010-05-27 23:11:57 +00:00
Dan Gohman
92ee877dcd Make ParseIRFile and getLazyIRFileModule incoporate the underlying 
error message string into their own error message string, so that
the information isn't lost.

llvm-svn: 104887
 2010-05-27 20:47:38 +00:00
Dan Gohman
d13e45d0ec Don't special-case stdout in llvm::WriteBitcodeToFile; just consider 
it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.

llvm-svn: 104878
 2010-05-27 20:06:51 +00:00
Jim Grosbach
0ff473d68a hook ISD::STACKADDR to an intrinsic 
llvm-svn: 104869
 2010-05-27 18:52:11 +00:00
Jim Grosbach
c2c7753f15 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862
 2010-05-27 18:23:48 +00:00
Dan Gohman
9789093ab7 Add basic error checking to MemoryBuffer::getSTDIN. 
llvm-svn: 104855
 2010-05-27 17:31:51 +00:00
Jim Grosbach
73ce6687df remove incorrect GCCBuiltin<> usage 
llvm-svn: 104833
 2010-05-27 15:04:02 +00:00
Gabor Greif
d8e3e9f572 typo 
llvm-svn: 104832
 2010-05-27 09:48:47 +00:00
Dan Gohman
0b5922b032 Fix Lint printing warnings multiple times. Remove the ErrorStr 
option from lintModule, which was an artifact from being
based on Verifier code.

llvm-svn: 104765
 2010-05-26 22:28:53 +00:00
Daniel Dunbar
bf243d9440 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

llvm-svn: 104747
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
 2010-05-26 21:47:28 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Bill Wendling
fbe85886bb Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by 
more than just the stack slot coloring algorithm.

llvm-svn: 104722
 2010-05-26 19:46:12 +00:00
Dan Gohman
616845c384 Eliminate the use of PriorityQueue and just use a std::vector, 
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
 2010-05-26 18:52:00 +00:00
Dan Gohman
3391366b42 Fix indentation. 
llvm-svn: 104717
 2010-05-26 18:37:48 +00:00
Daniel Dunbar
1b8e1aafae MC: Change RelaxInstruction to only take the input and output instructions. 
llvm-svn: 104713
 2010-05-26 18:15:06 +00:00
Daniel Dunbar
77240e2337 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

llvm-svn: 104707
 2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Daniel Dunbar
87dcbd1ee5 MC: Eliminate MCAsmFixup, replace with MCFixup. 
llvm-svn: 104699
 2010-05-26 15:18:56 +00:00
Daniel Dunbar
fe22195ea6 MC: Simplify MCFixup and increase the available offset size. 
llvm-svn: 104698
 2010-05-26 15:18:40 +00:00
Daniel Dunbar
55c1bf55fe MC: Use accessors for access to MCAsmFixup. 
llvm-svn: 104697
 2010-05-26 15:18:31 +00:00
Daniel Dunbar
a06aa279f4 MC: Eliminate MCFragment vtable, which was unnecessary. 
llvm-svn: 104689
 2010-05-26 06:50:57 +00:00
Eric Christopher
13ac28ede3 Temporarily revert r104655 as it's breaking the bots. 
llvm-svn: 104664
 2010-05-26 01:59:55 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman
ba28c900a2 Delete an unused function. 
llvm-svn: 104658
 2010-05-26 00:56:27 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Eric Christopher
371732bd2a Start adding mach-o tls reloc support. 
llvm-svn: 104651
 2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen
41388819f1 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
llvm-svn: 104650
 2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
9210d3b189 Print symbolic SubRegIndex names on machine operands. 
llvm-svn: 104628
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00