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Author SHA1 Message Date
Jakob Stoklund Olesen
bc000bf219 Prevent remat of partial register redefinitions. 
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
 2011-09-01 17:18:50 +00:00
Evan Cheng
6f4f659df2 Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690 
llvm-svn: 138934
 2011-09-01 01:45:00 +00:00
Bill Wendling
196167f986 Update to new EH scheme. 
llvm-svn: 138933
 2011-09-01 01:28:25 +00:00
Bill Wendling
a6d17107f5 Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are. 
llvm-svn: 138932
 2011-09-01 01:28:11 +00:00
Bill Wendling
d984ff9663 Submitted this too early. 
llvm-svn: 138931
 2011-09-01 01:18:33 +00:00
Bill Wendling
37fc90ccd9 Don't DCE the landingpad instruction. 
The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930
 2011-09-01 01:16:58 +00:00
Bill Wendling
68ada987a1 Update to new EH scheme. 
llvm-svn: 138928
 2011-09-01 01:08:21 +00:00
Bill Wendling
6ebcfea89e Update to new EH scheme. 
llvm-svn: 138927
 2011-09-01 01:02:41 +00:00
Bill Wendling
0b2e131798 Update some tests to the new EH scheme. 
llvm-svn: 138925
 2011-09-01 00:58:03 +00:00
Andrew Trick
e5d7c0d111 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Bill Wendling
220f6a3b14 Don't forget to add the landingpad and resume instructions to the InstructionList. 
This was found via a nightly build of 483.xalancbmk.

llvm-svn: 138923
 2011-09-01 00:50:20 +00:00
Jim Grosbach
2b04342a91 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Chad Rosier
aa490636db Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Bill Wendling
f3c35d972d Reenable test. 
llvm-svn: 138916
 2011-08-31 23:08:05 +00:00
Bill Wendling
fc2565227c Revert accidental commit 
llvm-svn: 138915
 2011-08-31 23:07:46 +00:00
Eli Friedman
5e68a0aca8 Disable this test until Bill fixes it properly. 
llvm-svn: 138914
 2011-08-31 23:03:30 +00:00
Jim Grosbach
1af1d2dfda Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Owen Anderson
dd71d9efb9 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
Bill Wendling
8b764c6aa5 Update to new EH scheme. 
llvm-svn: 138908
 2011-08-31 21:50:07 +00:00
Bill Wendling
e540c593ec Update to new EH scheme. 
llvm-svn: 138906
 2011-08-31 21:44:24 +00:00
Bill Wendling
66b613c8b9 Remove old declare statements. 
llvm-svn: 138905
 2011-08-31 21:41:20 +00:00
Bill Wendling
78fdf13f12 Update more tests to the new EH scheme. 
llvm-svn: 138904
 2011-08-31 21:40:15 +00:00
Bill Wendling
aca68bbe94 Update more tests to the new EH scheme. 
llvm-svn: 138903
 2011-08-31 21:39:05 +00:00
Eli Friedman
da555beef1 Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications). 
llvm-svn: 138902
 2011-08-31 21:37:06 +00:00
David Greene
bff3eae46b Fix Size Typing 
Stores sizes as uint64_t to avoid possible truncation.

llvm-svn: 138901
 2011-08-31 21:34:20 +00:00
Bill Wendling
da12f7322a Revert r138894. This was failing on cmake-clang-i686-msvc10. 
llvm-svn: 138900
 2011-08-31 21:20:25 +00:00
Jim Grosbach
3dd66f0c98 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Bruno Cardoso Lopes
8771512b75 Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS 
llvm-svn: 138897
 2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
22aceefbf7 Move MOVAPS,MOVUPS patterns close to the instructions definition 
llvm-svn: 138896
 2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
4823fe07e6 Remove "_Int" forms of MOVUPSmr and MOVAPSmr 
llvm-svn: 138895
 2011-08-31 21:15:22 +00:00
Bill Wendling
722de8a9aa Update more tests to the new EH scheme. 
llvm-svn: 138894
 2011-08-31 21:04:11 +00:00
Bill Wendling
7014c485f5 Update the tests to the new EH scheme. 
llvm-svn: 138891
 2011-08-31 20:55:40 +00:00
Bill Wendling
df24e0d185 Make sure we aren't deleting the landingpad instruction. 
The landingpad instruction is required in the landing pad block. Because we're
not deleting terminating instructions, the invoke may still jump to here (see
Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad
instruction, but keep it around until code-gen can remove the basic block.

llvm-svn: 138890
 2011-08-31 20:55:20 +00:00
Owen Anderson
4024b91dbe Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Eli Friedman
f57df1ac66 Misc cleanup; addresses Duncan's comments on r138877. 
llvm-svn: 138887
 2011-08-31 20:13:26 +00:00
Owen Anderson
de17548520 When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>

llvm-svn: 138885
 2011-08-31 20:00:11 +00:00
Jim Grosbach
506f8078a8 Run the Thumb1 parser tests in Thumb2 mode, as well. 
Thumb2 is a superset of Thumb1, so all of the encodings should still work.

llvm-svn: 138883
 2011-08-31 19:50:28 +00:00
Jim Grosbach
74f916342a Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Eli Friedman
5f0e04a5bd Fill in type legalization for MERGE_VALUES in all the various cases. Patch by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) 
llvm-svn: 138877
 2011-08-31 18:36:04 +00:00
Jim Grosbach
98ba1f40ee Thumb NOP encoding varies depending on ARCH revision. 
llvm-svn: 138876
 2011-08-31 18:35:46 +00:00
Owen Anderson
f30633abbf Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Jim Grosbach
4dddfb237c tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Eli Friedman
8ae6a88723 Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. 
llvm-svn: 138872
 2011-08-31 18:26:09 +00:00
Jim Grosbach
a2f9012605 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Devang Patel
26f7aeed7c After r138010, subroutine type does not have context info. Update type verifier accordingly. 
This fixes ptype.exp gdb testsuite regressions.

llvm-svn: 138869
 2011-08-31 18:04:31 +00:00
Eli Friedman
5d3814e0c4 64-bit atomic cmpxchg for ARM. 
llvm-svn: 138868
 2011-08-31 17:52:22 +00:00
Akira Hatanaka
6617606549 Fix typo. Patch by Liu. 
llvm-svn: 138866
 2011-08-31 17:49:04 +00:00
David Greene
a975ef3213 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864
 2011-08-31 17:30:56 +00:00
Jim Grosbach
a4c1e9d88a Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
ad3a292ff7 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861
 2011-08-31 17:00:02 +00:00