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173831 Commits

Author SHA1 Message Date
James Henderson
bd0abc721b [llvm-readobj][ELF]Add demangling support
This change adds demangling support to the ELF side of llvm-readobj,
under the switch --demangle/-C.

The following places are demangled: symbol table dumps (static and
dynamic), relocation dumps (static and dynamic), addrsig dumps, call
graph profile dumps, and group section signature symbols.

Although GNU readelf doesn't support demangling, it is still a useful
feature to have, and brings it on a par with llvm-objdump's
capabilities.

This fixes https://bugs.llvm.org/show_bug.cgi?id=40054.

Reviewed by: grimar, rupprecht

Differential Revision: https://reviews.llvm.org/D56791

llvm-svn: 351450
2019-01-17 15:34:12 +00:00
James Henderson
ccbf0e437b Move demangling function from llvm-objdump to Demangle library
This allows it to be used in an upcoming llvm-readobj change.

A small change in internal behaviour of the function is to always call
the microsoftDemangle function if the string does not have an itanium
encoding prefix, rather than only if it starts with '?'. This is
harmless because the microsoftDemangle function does the same check
already.

Reviewed by: grimar, erik.pilkington

Differential Revision: https://reviews.llvm.org/D56721

llvm-svn: 351448
2019-01-17 15:18:44 +00:00
Hans Wennborg
c466a75471 build_llvm_package.bat: Run more tests
llvm-svn: 351436
2019-01-17 13:11:15 +00:00
Max Kazantsev
790a9e98ac [LoopSimplifyCFG] Form LCSSA when a parent loop becomes a sibling
During the transforms in LoopSimplifyCFG, when we remove a dead exiting edge, the
parent loop may stop being reachable from the child loop, and therefore they become
siblings. If the former child loop had uses of some values from its former parent loop,
now such uses will require LCSSA Phis, even if they weren't needed before. So we must
form LCSSA for all loops that stopped being ancestors of the current loop in this case.

Differential Revision: https://reviews.llvm.org/D56144
Reviewed By: fedor.sergeev

llvm-svn: 351434
2019-01-17 12:51:10 +00:00
Max Kazantsev
09052af6c2 [LoopSimplifyCFG] Fix order of deletion of complex dead subloops
Function `DeleteDeadBlock` requires that all predecessors of a block
being deleted have already been deleted, with the exception of a
single-block loop. When we use it for removal of dead subloops that
contain more than one block, we may not fulfull this requirement and
fail an assertion.

This patch replaces invocation of `DeleteDeadBlock` with a generalized
version `DeleteDeadBlocks` that is able to deal with multiple dead blocks,
even if they contain some cycles.

Differential Revision: https://reviews.llvm.org/D56121
Reviewed By: fedor.sergeev

llvm-svn: 351433
2019-01-17 12:25:40 +00:00
Simon Pilgrim
f7ba65d569 [X86][SSE] Add PR40340 test case
llvm-svn: 351430
2019-01-17 11:20:23 +00:00
Simon Pilgrim
91155d4067 [X86] Add AVX512 test to insertps
Pre-commit for PR40340

llvm-svn: 351429
2019-01-17 11:11:15 +00:00
Matt Arsenault
416efa3eb6 GlobalISel: Add comment to clarify G_BUILD_VECTOR
llvm-svn: 351428
2019-01-17 10:50:07 +00:00
Matt Arsenault
afd1f8cb4f Allow FP types for atomicrmw xchg
llvm-svn: 351427
2019-01-17 10:49:01 +00:00
Benjamin Kramer
04b4351561 [MC] Remove unused variable
llvm-svn: 351426
2019-01-17 10:25:18 +00:00
Diana Picus
aa9082cd09 Fix capitalization. NFC
llvm-svn: 351425
2019-01-17 10:11:59 +00:00
Diana Picus
b99810417e [ARM GlobalISel] Allow calls to varargs functions
Allow varargs functions to be called, both in arm and thumb mode. This
boils down to choosing the correct calling convention, which we can
easily test by making sure arm_aapcscc is used instead of
arm_aapcs_vfpcc when the callee is variadic.

llvm-svn: 351424
2019-01-17 10:11:55 +00:00
Alex Bradbury
dcf62df83b [RISCV] Add codegen support for RV64A
In order to support codegen RV64A, this patch:
* Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg
  that use the i64 type. These are ultimately lowered to masked operations
  using lr.w/sc.w, but we need to use these alternate intrinsics for RV64
  because i32 is not legal
* Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and
  PseudoCmpXchg64
* Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as
  needed for RV64 and to select the i64 intrinsic IDs when necessary
* Adds appropriate patterns to RISCVInstrInfoA.td
* Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support

This ends up being a fairly mechanical change, as the logic for RV32A is
effectively reused.

Differential Revision: https://reviews.llvm.org/D53233

llvm-svn: 351422
2019-01-17 10:04:39 +00:00
Sanjin Sijaric
fc413edf7f [ARM64][Windows] Share unwind codes between epilogues
There are cases where we have multiple epilogues that have the exact same unwind
code sequence.  In that case, the epilogues can share the same unwind codes in
the .xdata section.  This should get us past the assert "SEH unwind data
splitting not yet implemented" in many cases.

We still need to add support for generating multiple .pdata/.xdata sections for
those functions that need to be split into fragments.

Differential Revision: https://reviews.llvm.org/D56813

llvm-svn: 351421
2019-01-17 09:45:17 +00:00
George Rimar
94ab87488c [llvm-objdump] - Fix comment. NFC.
Forgot to address this one.

llvm-svn: 351418
2019-01-17 09:14:33 +00:00
George Rimar
6b3ecc0c1d [llvm-objdump] - Simplify the getRelocationValueString. NFCI.
This refactors the getRelocationValueString method.
It is a bit overcomplicated and it is possible to reduce it without
losing the functionality it seems.

Differential revision: https://reviews.llvm.org/D56778

llvm-svn: 351417
2019-01-17 09:13:17 +00:00
Max Kazantsev
51a580322e [NFC] Factor out some local vars
llvm-svn: 351416
2019-01-17 06:20:42 +00:00
Thomas Lively
c66efefd0f [WebAssembly] Parse llvm.ident into producers section
llvm-svn: 351413
2019-01-17 02:29:55 +00:00
Vedant Kumar
f667646768 [MergeFunc] Prevent silent miscompile of vararg functions
The function merging pass miscompiles identical vararg functions. The
forwarding thunk it emits doesn't forward the full variable-length list
of arguments. Disable merging for vararg functions for now.

I've filed llvm.org/PR40345 to track the issue.

rdar://47326238

llvm-svn: 351411
2019-01-17 02:15:05 +00:00
Thomas Lively
27982aa1e1 Revert "[WebAssembly] Parse llvm.ident into producers section"
This reverts commit eccdbba3a02a33e13b5262e92200a33e2ead873d.

llvm-svn: 351410
2019-01-17 00:39:49 +00:00
Craig Topper
053e668d70 [X86] Remove GCCBuiltin from deprecated avx512 scatter intrinsics that use scalar integers for mask.
We will custom emit these builtins in clang using the new intrinsics that take a vXi1 mask.

llvm-svn: 351407
2019-01-17 00:34:04 +00:00
Eli Friedman
56856136ee [docs] Fix formatting.
llvm-svn: 351406
2019-01-17 00:31:35 +00:00
Vedant Kumar
92b9c60014 [FunctionComparator] Consider tail call kinds
Essentially, do not treat `call` and `musttail call` as the same thing.

As a drive-by, fold CallInst and InvokeInst handling together using the
CallSite helper.

Differential Revision: https://reviews.llvm.org/D56815

llvm-svn: 351405
2019-01-17 00:29:14 +00:00
Sanjin Sijaric
10c2d07dfd [SEH] [ARM64] Retrieve the frame pointer from SEH funclets
The Windows ARM64 runtime passes the establisher frame to funclets as the first
argument.

llvm-svn: 351404
2019-01-17 00:24:38 +00:00
Eli Friedman
86764a8220 [docs] Add more ARM/AArch64 links to CompilerWriterInfo.rst .
Also, fix a few existing links so they don't require registration.

llvm-svn: 351403
2019-01-17 00:21:08 +00:00
Thomas Lively
30a5c9786a [WebAssembly] Parse llvm.ident into producers section
Summary:
Everything before the word "version" is the tool, and everything after
the word "version" is the version.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56742

llvm-svn: 351399
2019-01-16 23:46:14 +00:00
Wei Mi
7f4ac5dfb0 Fix a mistake in rL351392.
PGOInstrGen should be initialized to "" instead of false.

llvm-svn: 351397
2019-01-16 23:31:40 +00:00
Jonas Devlieghere
b40a1a95fe [AsmPrinter] Collapse .loc 0 0 directives
Currently we do not always collapse subsequent .loc 0 0 directives. The
reason is that we were checking for a PrevInstLoc which is not set when
we emit a line-0 record. We should only check the LastAsmLine, which
seems to be created exactly for this purpose.

  // When we emit a line-0 record, we don't update PrevInstLoc; so look at
  // the last line number actually emitted, to see if it was line 0.
  unsigned LastAsmLine =
    Asm->OutStreamer->getContext().getCurrentDwarfLoc().getLine();

Differential revision: https://reviews.llvm.org/D56767

llvm-svn: 351395
2019-01-16 23:26:29 +00:00
Wei Mi
c317b3b823 [PGO] Make pgo related options in opt more consistent.
Currently we have pgo options defined in PassManagerBuilder.cpp only for
instrument pgo, but not for sample pgo. We also have pgo options defined
in NewPMDriver.cpp in opt only for new pass manager and for all kinds of
pgo. They have some inconsistency.

To make the options more consistent and make tests writing easier, the
patch let old pass manager to share the same pgo options with new pass
manager in opt, and removes the options in PassManagerBuilder.cpp.

Differential Revision: https://reviews.llvm.org/D56749

llvm-svn: 351392
2019-01-16 23:19:02 +00:00
Craig Topper
42fd10fac4 [X86] Remove GCCBuiltin from deprecated gather builtins in preparation for custom handling in clang.
llvm-svn: 351389
2019-01-16 22:34:24 +00:00
Sam Clegg
1ef2c042ad [WebAssembly] Remove expected failure from known_gcc_test_failures.txt. NFC.
Differential Revision: https://reviews.llvm.org/D56809

llvm-svn: 351388
2019-01-16 22:26:59 +00:00
JF Bastien
36109c9464 [NFC] Factor out + document build requirements
Summary: This change factors out compiler checking / warning, and documents LLVM_FORCE_USE_OLD_TOOLCHAIN. It doesn't introduce any functional changes nor policy changes, these will come late.

Subscribers: mgorny, jkorous, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56799

llvm-svn: 351387
2019-01-16 22:22:38 +00:00
Philip Pfaffe
47b1a19746 [TSan] Fix comment. NFC.
llvm-svn: 351386
2019-01-16 22:08:42 +00:00
Reid Kleckner
ee3d7ef6d6 [X86] Sink complex MCU CC helper to .cpp file from .h file, NFC
llvm-svn: 351384
2019-01-16 22:05:36 +00:00
Craig Topper
bae7415b04 [X86] Add X86ISD::VSHLV and X86ISD::VSRLV nodes for psllv and psrlv
Previously we used ISD::SHL and ISD::SRL to represent these in SelectionDAG. ISD::SHL/SRL interpret an out of range shift amount as undefined behavior and will constant fold to undef. While the intrinsics are defined to return 0 for out of range shift amounts. A previous patch added a special node for VPSRAV to produce all sign bits.

This was previously believed safe because undefs frequently get turned into 0 either from the constant pool or a desire to not have a false register dependency. But undef is treated specially in some optimizations. For example, its ignored in detection of vector splats. So if the ISD::SHL/SRL can be constant folded and all of the elements with in bounds shift amounts are the same, we might fold it to single element broadcast from the constant pool. This would not put 0s in the elements with out of bounds shift amounts.

We do have an existing InstCombine optimization to use shl/lshr when the shift amounts are all constant and in bounds. That should prevent some loss of constant folding from this change.

Patch by zhutianyang and Craig Topper

Differential Revision: https://reviews.llvm.org/D56695

llvm-svn: 351381
2019-01-16 21:46:32 +00:00
Craig Topper
ce0da9c2af [X86] Use X86ISD::BLENDV for blendv intrinsics. Replace vselect with blendv just before isel table lookup. Remove vselect isel patterns.
This cleans up the duplication we have with both intrinsic isel patterns and vselect isel patterns. This should also allow the intrinsics to get SimplifyDemandedBits support for the condition.

I've switched the canonical pattern in isel to use the X86ISD::BLENDV node instead of VSELECT. Since it always seemed weird to move from BLENDV with its relaxed rules on condition bits to VSELECT which has strict rules about all bits of the condition element being the same. Its more correct to go from VSELECT to BLENDV.

Differential Revision: https://reviews.llvm.org/D56771

llvm-svn: 351380
2019-01-16 21:46:28 +00:00
Changpeng Fang
25c9efdee4 AMDGPU: Adjust the chain for loads writing to the HI part of a register.
Summary:
  For these loads that write to the HI part of a register, we should chain them to the op that writes to the LO part
of the register to maintain the appropriate order.

Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D56454

llvm-svn: 351379
2019-01-16 21:32:53 +00:00
Craig Topper
8e2e7a1d93 [X86] Add a one use check to the setcc inversion code in combineVSelectWithAllOnesOrZeros
If we're going to generate a new inverted setcc, we should make sure we will be able to remove the old setcc.

Differential Revision: https://reviews.llvm.org/D56765

llvm-svn: 351378
2019-01-16 21:29:29 +00:00
Craig Topper
5d7dc5530c [X86] Add test case for D56765. NFC
llvm-svn: 351377
2019-01-16 21:29:26 +00:00
Nikita Popov
c0f210706a [X86] Add additional saturating add/sub vector tests; NFC
Additional tests for vNi32 and vNi64. I've added these for
usub.sat before, this covers uadd.sat, ssub.sat and sadd.sat.

llvm-svn: 351375
2019-01-16 20:53:23 +00:00
Nico Weber
a042271911 Fix most of LLVM's tests with LLVM_ENABLE_PIC=OFF
Lots of tests rely on llvm-lto being present, but LLVM_ENABLE_PIC=OFF currently
disables building that executable.

There's no reason for not building llvm-lto with LLVM_ENABLE_PIC=OFF so just
build it. r191042 moved it into a "if (!WIN)" block at the time, and then
211852 made that "if(NOT CYGWIN AND LLVM_ENABLE_PIC)" -- but that's only needed
for LTO (the ld64 plugin), not for the llvm-lto binary.

Differential Revision: https://reviews.llvm.org/D56801

llvm-svn: 351374
2019-01-16 20:44:36 +00:00
Mandeep Singh Grang
9f9869fa2f [COFF, ARM64] Implement support for SEH extensions __try/__except/__finally
Summary:
This patch supports MS SEH extensions __try/__except/__finally. The intrinsics localescape and localrecover are responsible for communicating escaped static allocas from the try block to the handler.

We need to preserve frame pointers for SEH. So we create a new function/property HasLocalEscape.

Reviewers: rnk, compnerd, mstorsjo, TomTan, efriedma, ssijaric

Reviewed By: rnk, efriedma

Subscribers: smeenai, jrmuizel, alex, majnemer, ssijaric, ehsan, dmajor, kristina, javed.absar, kristof.beyls, chrib, llvm-commits

Differential Revision: https://reviews.llvm.org/D53540

llvm-svn: 351370
2019-01-16 19:52:59 +00:00
Krzysztof Parzyszek
6e2dddb656 [Hexagon] Do not promote terminator instructions in Hexagon loop idioms
llvm-svn: 351369
2019-01-16 19:40:27 +00:00
Peter Collingbourne
0e57b6e44c gn build: Add headers to compiler-rt build files.
Also fix sort order in llvm/lib/CodeGen/GlobalISel/BUILD.gn.

llvm-svn: 351367
2019-01-16 18:45:12 +00:00
Andrea Di Biagio
112377135a [X86][BtVer2] Update latency of horizontal operations.
On Jaguar, horizontal adds/subs have local forwarding disable.
That means, we pay a compulsory extra cycle of write-back stage, and the value
is not available until the end of that stage.

This patch changes the latency of horizontal operations by adding an extra
cycle. With this patch, latency numbers now match what is reported by perf.

I plan to send another patch to also 'fix' the latency of shuffle operations (on
Jaguar, local forwarding is disabled for vector shuffles too).

Differential Revision: https://reviews.llvm.org/D56777

llvm-svn: 351366
2019-01-16 18:18:01 +00:00
Simon Pilgrim
d9a7e043f6 [X86] getFauxShuffleMask - bail for non-byte aligned shuffle types
Remove the existing assertion and just return false for unexpected shuffle value types (<X x i1> mainly....).

Found while updating combineX86ShufflesRecursively to run within SimplifyDemandedVectorElts/SimplifyDemandedBits.

llvm-svn: 351365
2019-01-16 18:15:31 +00:00
Simon Pilgrim
5a80c180db [X86] Regenerate test
Split check-prefixes to support a future commit

llvm-svn: 351362
2019-01-16 18:00:09 +00:00
Armando Montanez
2e2a5f703a [elfabi] Add support for reading DT_SONAME from binaries
This change gives the llvm-elfabi tool the ability to read DT_SONAME from a binary ELF file into an ELFStub.

Added:

 - DynamicEntries struct for storing dynamic entries that are relevant to elfabi.
 - terminatedSubstr() retrieves a null-terminated substring from a StringRef.
 - appendToError() appends a string to an error, allowing more specific error messages.

Differential Revision: https://reviews.llvm.org/D55629

llvm-svn: 351361
2019-01-16 17:47:16 +00:00
Jeremy Morse
32db970afc [DebugInfo] Allow creation of DBG_VALUEs in blocks where the operand is not used
dbg.value intrinsics can appear in blocks where their operand is not used,
meaning the operand never receives an SDNode, and thus no DBG_VALUE will
be created. Get around this by looking to see whether the operand has already
been allocated a virtual register. This allows dbg.values of Phi node and
Values that are used across basic blocks to successfully be translated into
DBG_VALUEs.

Differential Revision: https://reviews.llvm.org/D56678

llvm-svn: 351358
2019-01-16 17:25:27 +00:00
Erich Keane
2a4517ad85 Remove misleading line about git's lack of revision numbers.
Change-Id: I8a22cb4b4bef9bceee1f43381435d664c2cfd770
llvm-svn: 351357
2019-01-16 16:59:11 +00:00