Chris Lattner
15ac62827e
Add immediate forms of in/out. Use let to shorten lines
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llvm-svn: 12895
2004-04-13 17:19:31 +00:00
Chris Lattner
43f754339a
Fix issues that the local allocator has dealing with instructions that implicitly use ST(0)
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llvm-svn: 12855
2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518
No really, fix printing for LLC. I gotta get a way for CVS to whine at me if
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I have unsaved emacs buffers, geeze...
llvm-svn: 12854
2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8
Correct printing for LLC and the encoding for the JIT
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llvm-svn: 12853
2004-04-12 01:50:04 +00:00
Chris Lattner
cfb7144bf1
Add two new instructions
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llvm-svn: 12850
2004-04-12 01:38:55 +00:00
Chris Lattner
dda382531e
Add some new instructions
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llvm-svn: 12838
2004-04-11 20:24:15 +00:00
John Criswell
8740c3767d
Changes recommended by Chris:
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InstSelectSimple.cpp:
Change the checks for proper I/O port address size into an exit() instead
of an assertion. Assertions aren't used in Release builds, and handling
this error should be graceful (not that this counts as graceful, but it's
more graceful).
Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
Added the OpSize attribute to the 16 bit IN and OUT instructions.
llvm-svn: 12786
2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
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I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
llvm-svn: 12782
2004-04-08 20:31:47 +00:00
Chris Lattner
993d6106c7
Fix incorrect encoding of some ADC and SBB instuctions
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llvm-svn: 12710
2004-04-06 19:20:32 +00:00
Chris Lattner
e84f12a165
The sbb instructions really ARE sbb's, not adc's
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llvm-svn: 12682
2004-04-06 02:02:11 +00:00
Alkis Evlogimenos
85e007a6dc
Fix type in comments
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llvm-svn: 12611
2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
20b074682c
Add more ADC and SBB variants
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llvm-svn: 12607
2004-04-02 07:11:10 +00:00
Chris Lattner
e4fa3010db
Add FP conditional move instructions, which annoyingly have special properties
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that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
llvm-svn: 12574
2004-03-31 22:02:13 +00:00
Chris Lattner
57968a98df
Fix some serious bugs in the cmov descriptions, which didn't cause a problem because
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we never generated them
Make indentation a bit more consistent
llvm-svn: 12549
2004-03-30 20:18:02 +00:00
Alkis Evlogimenos
6ac147a7fb
Add LAHF instruction
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llvm-svn: 12424
2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
da990ad8a4
Add support for a wider range of CMOV instructions.
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llvm-svn: 12336
2004-03-12 17:59:56 +00:00
Alkis Evlogimenos
7c0224327e
Differentiate between extended precision floats (80-bit) and double precision floats (64-bit)
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llvm-svn: 12254
2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
65649a50e9
Add memory operand version of conditional move.
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llvm-svn: 12190
2004-03-07 03:19:11 +00:00
Alkis Evlogimenos
8d8f872b3d
Use correct template for SHLD and SHRD instructions so that the memory
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operand size is correctly specified.
llvm-svn: 11997
2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
7ecfe0a839
A big X86 instruction rename. The instructions are renamed to make
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their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
llvm-svn: 11995
2004-02-29 08:50:03 +00:00
Alkis Evlogimenos
0f96b44e0e
Use correct template for ADC instruction with memory operands.
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llvm-svn: 11974
2004-02-29 02:18:17 +00:00
Alkis Evlogimenos
6815402082
SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
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to denote this fact.
llvm-svn: 11972
2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43
Floating point loads/stores act on memory operands. Rename them to
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denote this fact.
llvm-svn: 11971
2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9
Rename instruction templates to be easier to the human eye to
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parse. The name is now I (operand size)*. For example:
Im32 -> instruction with 32-bit memory operands.
Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
operands.
llvm-svn: 11970
2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
f208a0fd81
Each instruction now has both an ImmType and a MemType. This describes
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the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
llvm-svn: 11967
2004-02-28 22:02:05 +00:00
Alkis Evlogimenos
977dbaadf7
Do not generate instructions with mismatched memory/immediate sized
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operands. The X86 backend doesn't handle them properly right now.
llvm-svn: 11944
2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7
Further comment updates.
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llvm-svn: 11933
2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160
Update comments.
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llvm-svn: 11932
2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0
My previous commit broke the jit. The shift instructions always take
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an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.
A bug still exists:
def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.
llvm-svn: 11931
2004-02-28 02:56:26 +00:00
Alkis Evlogimenos
ace6d81654
Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
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instructions.
llvm-svn: 11923
2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d
Fix encoding of ADD and SUB family of instructions. Also rearrange
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them so that they are consistent with AND, XOR, etc...
llvm-svn: 11922
2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23
Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
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llvm-svn: 11921
2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
5ac109957f
Add memory operand folding support for the SETcc family of
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instructions.
llvm-svn: 11907
2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9
Add memory operand folding support for SHLD and SHRD instructions.
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llvm-svn: 11905
2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741
Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
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llvm-svn: 11903
2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2
Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
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consistent with the rest and also pepare for the addition of their
memory operand variants.
llvm-svn: 11902
2004-02-27 06:57:05 +00:00
Chris Lattner
f9acb33dfd
Add a new cmove instruction
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llvm-svn: 11722
2004-02-23 01:16:05 +00:00
Alkis Evlogimenos
7ec1bad952
Fix argument size for MOVSX and MOVZX instructions.
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llvm-svn: 11576
2004-02-18 16:20:40 +00:00
Alkis Evlogimenos
c6f0651e5c
These store to memory too.
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llvm-svn: 11558
2004-02-17 17:53:48 +00:00
Chris Lattner
88271db3bc
These store to memory, not read from it.
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llvm-svn: 11556
2004-02-17 17:46:50 +00:00
Alkis Evlogimenos
b815fd46ec
Add TEST and XCHG memory operand support.
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llvm-svn: 11550
2004-02-17 15:48:42 +00:00
Alkis Evlogimenos
32a5b0fd6c
Add OR and XOR memory operand support.
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llvm-svn: 11549
2004-02-17 15:33:14 +00:00
Alkis Evlogimenos
135c4faa55
Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT,
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MOVSX, and MOVZX.
llvm-svn: 11546
2004-02-17 09:14:23 +00:00
Alkis Evlogimenos
d7e3cc8d65
Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions.
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llvm-svn: 11544
2004-02-17 08:49:00 +00:00
Alkis Evlogimenos
638db7b5aa
Add SUB{rm,mr,mi}{8,16,32} instructions.
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llvm-svn: 11543
2004-02-17 08:17:40 +00:00
Alkis Evlogimenos
28691e063b
Add support for ADC{rm.mr}32 and SBB{rm,mr}32.
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llvm-svn: 11540
2004-02-17 08:06:31 +00:00
Chris Lattner
d4b2f4ef32
Fix the mneumonics for the mov instructions to have the source and destination
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order in the correct sense!! Arg!
llvm-svn: 11530
2004-02-17 06:28:19 +00:00
Chris Lattner
5757579731
Fix the last crimes against nature that used the 'ir' ordering to use the
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'ri' ordering instead... no it's not possible to store a register into an
immediate!
llvm-svn: 11529
2004-02-17 06:24:02 +00:00
Chris Lattner
16666f8bd2
Rename MOVi[mr] instructions to MOV[rm]i
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llvm-svn: 11527
2004-02-17 06:16:44 +00:00
Chris Lattner
9751eb8ab9
Add mem forms of AND instructions
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llvm-svn: 11521
2004-02-17 05:25:50 +00:00
Chris Lattner
3c514e8a54
Rename the IMULri* instructions to IMULrri, as they are actually three address
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instructions. Add forms of these instructions that read from memory
llvm-svn: 11518
2004-02-17 04:26:43 +00:00
Alkis Evlogimenos
657876c656
Add two more variants of add. Update comments.
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llvm-svn: 11510
2004-02-16 23:48:42 +00:00
Chris Lattner
d8cc48da34
Add some ADD instructions that take memory operands for Alkis
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llvm-svn: 11502
2004-02-16 18:19:31 +00:00
Chris Lattner
cc5bf36481
Add support for the 'pop' instruction
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llvm-svn: 11451
2004-02-14 21:06:02 +00:00
Chris Lattner
c87772961e
Urg, right. These need an input value...
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llvm-svn: 11443
2004-02-14 04:47:23 +00:00
Chris Lattner
6890963e48
add 'rep stos[bwd]' instructions
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llvm-svn: 11441
2004-02-14 04:45:37 +00:00
Chris Lattner
d1c4f4c833
Add support for the rep movs[bwd] instructions, and emit them when code
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generating the llvm.memcpy intrinsic.
llvm-svn: 11351
2004-02-12 17:53:22 +00:00
Alkis Evlogimenos
a5458ae146
IMULri* instructions do not require their first two registers operands
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to be the same (IOW they are not two address instructions).
llvm-svn: 11117
2004-02-04 17:21:04 +00:00
Chris Lattner
7b6e8f1f70
Add the ftst instruction
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llvm-svn: 11095
2004-02-03 07:27:50 +00:00
Chris Lattner
06f08a26ac
No need to declare implicit uses/defs of ST0
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llvm-svn: 11081
2004-02-02 19:57:45 +00:00
Chris Lattner
71c12c8e0d
Generate the fchs instruction to negate a floating point number
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llvm-svn: 11078
2004-02-02 19:31:38 +00:00
Alkis Evlogimenos
41bd8284e3
Remove floating point killer pass. This is now implemented in the
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instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.
llvm-svn: 10562
2003-12-20 16:22:59 +00:00
John Criswell
de34542f41
Added LLVM copyright header.
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llvm-svn: 9321
2003-10-21 15:17:13 +00:00
Chris Lattner
c4f8226aaf
Emit x86 instructions for: A = B op C, where A and B are 16-bit registers,
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C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.
This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version. Because these instructions are very common, this
can save a LOT of code space. For example, I sampled two benchmarks, 176.gcc
and 254.gap.
BM Old New Reduction
176.gcc 2673621 2548962 4.89%
254.gap 498261 475104 4.87%
Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc. Not bad.
Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.
llvm-svn: 9284
2003-10-20 05:53:31 +00:00
Chris Lattner
5a577c0b28
* Rename X86::IMULr16 -> X86::IMULrr16
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* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
extra copy into a register, reducing register pressure.
llvm-svn: 9278
2003-10-20 03:42:58 +00:00
Chris Lattner
57825f087d
Add some new instructions. Wheee
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llvm-svn: 9266
2003-10-19 19:25:35 +00:00
Chris Lattner
8d79ae7383
Add support for unconditional branches and for emitting JE instructions
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llvm-svn: 7872
2003-08-15 04:50:49 +00:00
Chris Lattner
be0530bab9
Add basic support for 16 and 32 bit function arguments!
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llvm-svn: 7755
2003-08-11 21:30:00 +00:00
Chris Lattner
1ecd1818a0
Add (ret int) expander so that we can at least write testcases
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llvm-svn: 7730
2003-08-11 15:48:00 +00:00
Chris Lattner
3f4b5cf09a
Add patterns for multiply, and, or, and xor
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llvm-svn: 7725
2003-08-11 15:23:25 +00:00
Chris Lattner
83831c66fc
add a pattern for RET, immediates no longer need to be explicitly typed
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llvm-svn: 7635
2003-08-06 15:31:35 +00:00
Chris Lattner
17fc21b5fa
This is the real fix for the previous register allocator problem.
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Physical registers should not float around.
llvm-svn: 7587
2003-08-05 00:48:47 +00:00
Chris Lattner
cf51f31c3e
Add patterns for (mov R, R) (mov R, I) and subtracts. The moves are to enable
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testing, the subtracts are because I was in the neighborhood.
llvm-svn: 7581
2003-08-04 21:18:19 +00:00
Chris Lattner
900d31f5ba
Change comments into something that TableGen can read!
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llvm-svn: 7580
2003-08-04 21:08:29 +00:00
Chris Lattner
0d7b042206
transition to using let instead of set
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llvm-svn: 7564
2003-08-04 04:59:56 +00:00
Chris Lattner
89b4a26e56
Add new TableGen instruction definitions
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llvm-svn: 7537
2003-08-03 21:54:21 +00:00