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Commit Graph

205871 Commits

Author SHA1 Message Date
LLVM GN Syncbot
c5ea71af15 [gn build] Port ce6900c6cb5 2020-10-27 19:40:29 +00:00
Fangrui Song
7a2f51933b [test] Make ThinLTO/X86/crash_debuginfo.ll work with -enable-new-pm=1
LegacyInlinerBase::doFinalization runs removeDeadFunctions() to remove bar but
the new PM inliner doesn't. Improve the test to use llvm-nm -U.
2020-10-27 12:37:19 -07:00
Nicolai Hähnle
84f0cc96e8 Revert multiple patches based on "Introduce CfgTraits abstraction"
These logically belong together since it's a base commit plus
followup fixes to less common build configurations.

The patches are:

Revert "CfgInterface: rename interface() to getInterface()"

This reverts commit a74fc481588fcea9317cbf1f6c5888a30c9edd2d.

Revert "Wrap CfgTraitsFor in namespace llvm to please GCC 5"

This reverts commit f2a06875b604c00cbe96e54363f4f5d28935d610.

Revert "Try to make GCC5 happy about the CfgTraits thing"

This reverts commit 03a5f7ce12e2111c8b7bc5a95cff4c51b516250f.

Revert "Introduce CfgTraits abstraction"

This reverts commit c0cdd22c72fab47a3c37b5a8401763995cadaa77.
2020-10-27 20:33:30 +01:00
Nicolai Hähnle
d9118fe9e0 Revert "DomTree: Extract (mostly) read-only logic into type-erased base classes"
This reverts commit 848a68a032d1c59274526abb3220714202d4757e.
2020-10-27 20:33:29 +01:00
Florian Hahn
3098b4b895 [llvm-reduce] Add test with some aliases. 2020-10-27 19:29:48 +00:00
Stanislav Mekhanoshin
2bb7f5cddb [AMDGPU] Change predicate for fma/fmac legacy
I do not exactly like the use of a negative predicate to
enable instructions' support. Change HasNoMadMacF32Insts
with HasFmaLegacy32.

Differential Revision: https://reviews.llvm.org/D90250
2020-10-27 12:03:52 -07:00
Victor Huang
aa4ee0ed67 [PowerPC][PCRelative] Turn on TLS support for PCRel by default
Turn on TLS support for PCRel by default and update the test cases.

Differential Revision: https://reviews.llvm.org/D88738
Reviewed by: stefanp, kamaub
2020-10-27 13:58:44 -05:00
Jay Foad
2a3c18dd52 [AMDGPU] Fix check prefix for VOP3 VI disassembler tests
Also, following D81841, don't try to encode f16 literals in i16/u16
instructions.

Differential Revision: https://reviews.llvm.org/D90242
2020-10-27 18:43:25 +00:00
Simon Pilgrim
a330db66de [llvm-readobj] Remove duplicate inner if() condition. NFCI.
This should have been removed when rG445c3fdd2ae8 simplified the conditions.

Reported as "Snippet 5" in https://www.viva64.com/en/b/0771/
2020-10-27 18:36:04 +00:00
Amy Huang
d210bc3179 Revert "[CodeView] Emit static data members as S_CONSTANTs."
Seems like there's an assert in here that we shouldn't be running into.

This reverts commit 515973222ed29abe49f241e89edb6854f44162d4.
2020-10-27 11:29:58 -07:00
LLVM GN Syncbot
05d3fe531a [gn build] Port 46c3d5cb05d 2020-10-27 18:08:19 +00:00
Michael Liao
18c2025616 [amdgpu] Add the late codegen preparation pass.
Summary:
- Teach that pass to widen naturally aligned but not DWORD aligned
  sub-DWORD loads.

Reviewers: rampitec, arsenm

Subscribers:

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80364
2020-10-27 14:07:59 -04:00
Simon Pilgrim
a9377f08e7 [X86] Regenerate scalar fptosi/fptoui tests. NFCI.
Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
2020-10-27 17:44:30 +00:00
Kazushi (Jam) Marukawa
3bb93cf4fa [VE] Add vector reduction instructions
Add VSUMS/VSUMX/VFSUM/VMAXS/VMAXX/VFMAX/VRAND/VROR/VRXOR isntructions.
Add regression tests too.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90227
2020-10-28 02:33:21 +09:00
Vedant Kumar
b89a1d3e52 [Utils] Skip RemoveRedundantDbgInstrs in MergeBlockIntoPredecessor (PR47746)
This patch changes MergeBlockIntoPredecessor to skip the call to
RemoveRedundantDbgInstrs, in effect partially reverting D71480 due to
some compile-time issues spotted in LoopUnroll and SimplifyCFG.

The call to RemoveRedundantDbgInstrs appears to have changed the
worst-case behavior of the merging utility. Loosely speaking, it seems
to have gone from O(#phis) to O(#insts).

It might not be possible to mitigate this by scanning a block to
determine whether there are any debug intrinsics to remove, since such a
scan costs O(#insts).

So: skip the call to RemoveRedundantDbgInstrs. There's surprisingly
little fallout from this, and most of it can be addressed by doing
RemoveRedundantDbgInstrs later. The exception is (the block-local
version of) SimplifyCFG, where it might just be too expensive to call
RemoveRedundantDbgInstrs.

Differential Revision: https://reviews.llvm.org/D88928
2020-10-27 10:12:59 -07:00
Sam McCall
25cd2447cf [ADT] Fix accidental pointer comparison in test 2020-10-27 18:11:45 +01:00
Simon Pilgrim
c4569f08c7 [X86] Regenerate xor tests. NFCI.
Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
2020-10-27 16:45:47 +00:00
Simon Pilgrim
4b200d97f1 [X86] Regenerate tbm intrinsics tests. NFCI.
Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
2020-10-27 16:45:47 +00:00
Simon Pilgrim
0bef6245da [X86] Regenerate popcnt tests. NFCI.
Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
2020-10-27 16:45:46 +00:00
Simon Pilgrim
b0dfafed55 [X86] Regenerate xop tests with common prefixes. 2020-10-27 16:45:46 +00:00
Yashaswini Hegde
40798dd5b1 [Flang][OpenMP 4.5] Add semantic check for OpenMP default clause 2020-10-27 12:38:47 -04:00
Jay Foad
2ab75283cb [AMDGPU] Add llvm.amdgcn.div.scale with fneg tests 2020-10-27 16:05:51 +00:00
Tony
f0f576d14d [AMDGPU] Add missing support for targets
- Add missing tests.

Differential Revision: https://reviews.llvm.org/D90212
2020-10-27 15:36:31 +00:00
Florian Hahn
34968e9ca6 [AArch64] Add additional tests for vector inserts with common element. 2020-10-27 14:58:56 +00:00
Raphael Isemann
80dc6586fb Revert "[IndVars] Remove monotonic checks with unknown exit count"
This reverts commit c6ca26c0bfedb8f80d6f8cb9adde25b1d6aac1c5.
This breaks stage2 builds due to hitting this assert:
```
   Assertion failed: (WeightSum <= UINT32_MAX && "Expected weights to scale down to 32 bits"), function calcMetadataWeights
```
when compiling AArch64RegisterBankInfo.cpp in LLVM.
2020-10-27 15:31:37 +01:00
Raphael Isemann
f3c8e5c597 Revert "[NFC] Factor away lambda's redundant parameter"
This reverts commit fdc845b36130d162e5a66e427bf69b2c37b6c6bb.
It seems to be a follow-up to c6372b3fb495 which will be reverted.
2020-10-27 15:30:52 +01:00
Michael Liao
ebdef472f9 [amdgpu] Enable use of AA during codegen.
- Add an internal option `-amdgpu-use-aa-in-codegen` to enable or
  disable this feature. By Default, it's enabled.

Differential Revision: https://reviews.llvm.org/D89320
2020-10-27 09:46:23 -04:00
Simon Pilgrim
ef550a5251 Revert rG0905bd5c2fa42bd4c "[InstCombine] collectBitParts - add trunc support."
This reverts commit 0905bd5c2fa42bd4c0e6e0aaa08b966f165b9dfa.

Causing failures in multistage buildbots that I need to investigate
2020-10-27 13:43:54 +00:00
Benjamin Kramer
b4071a353d [X86] Don't crash on CVTPS2PH with wide vector inputs. 2020-10-27 14:42:02 +01:00
Simon Pilgrim
60eeed7af0 [X86] Regenerate all-ones vector tests with common prefixes. 2020-10-27 13:41:27 +00:00
Nico Weber
1ea6033a22 Revert "Use uint64_t for branch weights instead of uint32_t"
This reverts commit e5766f25c62c185632e3a75bf45b313eadab774b.
Makes clang assert when building Chromium, see https://crbug.com/1142813
for a repro.
2020-10-27 09:26:21 -04:00
Simon Pilgrim
29e9d9a1e2 [X86] Regenerate vector shift tests. NFCI.
Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
2020-10-27 13:14:54 +00:00
Simon Pilgrim
3e4f2ad439 [InstCombine] collectBitParts - add trunc support.
This should allow us to remove the rather limited matchOrConcat fold and just use recognizeBSwapOrBitReverseIdiom.
2020-10-27 13:14:54 +00:00
Djordje Todorovic
d3e8393700 [NFC][IntrRefLDV] Some code clean up
As reading the source code, I've found some minor nits:
  -Use using instead of typedef
  -Fix a comment
  -Refactor

Differential Revision: https://reviews.llvm.org/D90155
2020-10-27 05:31:24 -07:00
Sven van Haastregt
a77c70490e [TargetLowering] Add i1 condition for bit comparison fold
For i1 types, boolean false is represented identically regardless of
the boolean content, so we can allow optimizations that otherwise
would not be correct for booleans with false represented as a negative
one.

Patch by Erik Hogeman.

Differential Revision: https://reviews.llvm.org/D90145
2020-10-27 12:22:20 +00:00
LLVM GN Syncbot
3188a13350 [gn build] Port 850325348ae 2020-10-27 12:17:41 +00:00
Alex Richardson
ab6e2d9347 [ValueTracking][NFC] Use Log2(Align) instead of countTrailingZeroes
The latter can probably be optimized to the same final code, but this might
help -O0 builds.
2020-10-27 12:16:45 +00:00
Alex Richardson
58c20890b0 [ValueTracking] Add more tests for alignment assume bundles
I noticed that alignment was no longer inferred as well after I last merged
our CHERI fork from upstream. I opened this review before seeing that D88669
already fixes the same problem, so this commit simply adds the new test that
I added as part of this change.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D89830
2020-10-27 12:16:45 +00:00
Shimin Cui
29a0e7a508 [ValueTracking] Add tracking of the alignment assume bundle
This patch is to add the support of the value tracking of the alignment assume bundle.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D88669
2020-10-27 12:16:45 +00:00
Sebastian Neubauer
d2b71753ac msgpack: Improve error for empty node 2020-10-27 12:57:00 +01:00
Roman Lebedev
49368a63f8 [InstCombine] Fold (X >>? C1) << C2 patterns to shift+bitmask (PR37872)
This is essentially finalizes a revert of rL155136,
because nowadays the situation has improved, SCEV can model
all these patterns well, and we canonicalize rotate-like patterns
into a funnel shift intrinsics in InstCombine.
So this should not cause any pessimization.

I've verified the canonicalize-{a,l}shr-shl-to-masking.ll transforms
with alive, which confirms that we can freely preserve exact-ness,
and no-wrap flags.

Profs:
* base: https://rise4fun.com/Alive/gPQ
* exact-ness preservation: https://rise4fun.com/Alive/izi
* nuw preservation: https://rise4fun.com/Alive/DmD
* nsw preservation: https://rise4fun.com/Alive/SLN6N
* nuw nsw preservation: https://rise4fun.com/Alive/Qp7

Refs. https://reviews.llvm.org/D46760
2020-10-27 14:42:53 +03:00
Roman Lebedev
27b5264858 [NFC][PhaseOrdering] Autogenerate basic.ll test 2020-10-27 14:42:53 +03:00
Roman Lebedev
ff2b16b568 [NFC][InstCombine] Autogenerate cast.ll test 2020-10-27 14:42:52 +03:00
Roman Lebedev
7c2811a760 [NFC][InstCombine] Add more exhaustive test coverage for (x >>? X1) << C2 pattern (PR37872) 2020-10-27 14:42:52 +03:00
Kazushi (Jam) Marukawa
7caf0af059 [VE] Add vector float instructions
Add VFAD/VFSB/VFMP/VFDV/VFSQRT/VFCP/VFCM/VFMAD/VFMSB/VFNMAD/VFNMSB/
VRCP/VRSQRT/VRSQRTNEX/VFIX/VFIXX/VFLT/VFLTX/VCVS/VCVD instructions.
Add regression tests too.  Also add additional AsmParser for VFIX
and VFIXX instructions to parse their mnemonic.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90166
2020-10-27 20:42:24 +09:00
Kazushi (Jam) Marukawa
aa30484b49 [VE] Add missing regression test
In the previous "Add vector shift instructions", I forgot to add
regression tests for VSRL and VSRD instructions.  This patch is
adding them.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90167
2020-10-27 20:40:30 +09:00
Georgii Rymar
4708221cf7 [llvm-readelf] - Implement --section-details option.
--section-details/-t is a GNU readelf option that produce
an output that is an alternative to --sections.

Differential revision: https://reviews.llvm.org/D89304
2020-10-27 13:29:39 +03:00
Med Ismail Bennani
a554ad6fde [llvm/DebugInfo] Simplify DW_OP_implicit_value condition (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-10-27 11:25:19 +01:00
Jay Foad
1e89a40c5d [AMDGPU] Use DPP instead of Ext in a couple of class names. NFC. 2020-10-27 10:22:30 +00:00
Georgii Rymar
76df633769 [yaml2obj] - Add a way to override the sh_addralign field of a section.
Imagine the following declaration of a section:
```
Sections:
  - Name:         .dynsym
    Type:         SHT_DYNSYM
    AddressAlign: 0x1111111111111111
```

The aligment is large and yaml2obj reports an error currently:
"the desired output size is greater than permitted. Use the --max-size option to change the limit"

This patch implements the "ShAddrAlign" key, which is similar to other "Sh*" keys we have.
With it it is possible to override the `sh_addralign` field, ignoring the writing of alignment bytes.

Differential revision: https://reviews.llvm.org/D90019
2020-10-27 13:03:38 +03:00