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Commit Graph

3152 Commits

Author SHA1 Message Date
Vladimir Medic
8272ae6789 This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file.
llvm-svn: 202807
2014-03-04 09:54:09 +00:00
Kevin Qin
8d741b5791 [AArch64]Fix improper diagnostics about offset range of load/store instructions.
llvm-svn: 202775
2014-03-04 02:05:13 +00:00
Reid Kleckner
ec58432880 MC: Fix Intel assembly parser for [global + offset]
We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

llvm-svn: 202774
2014-03-04 00:33:17 +00:00
Ed Maste
1644c2608f [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug data
This fixes invalid lengths in .debug_aranges on big-endian mips64
(lengths appear to be left-shifted by 32 bits) and in .debug_loc.

Differential Revision: http://llvm-reviews.chandlerc.com/D2517

llvm-svn: 202716
2014-03-03 14:27:49 +00:00
Vladimir Medic
c17b0032b0 This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
llvm-svn: 202706
2014-03-03 13:12:59 +00:00
Saleem Abdulrasool
ceb96bcf7f AsmParser: add missed tests
The diagnostics tests were missing from the previous introduction of ifeqs.

llvm-svn: 202674
2014-03-03 06:35:00 +00:00
Venkatraman Govindaraju
34b3409b1a [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
llvm-svn: 202670
2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju
773ff0c22b [Sparc] Add return/rett instruction to Sparc backend.
llvm-svn: 202666
2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju
b64b412386 [Sparc] Add support for decoding jmpl/retl/ret instruction.
llvm-svn: 202663
2014-03-02 21:17:44 +00:00
Venkatraman Govindaraju
bb48cf7681 [Sparc] Add fcmpe* instructions to Sparc backend.
llvm-svn: 202661
2014-03-02 19:56:19 +00:00
Venkatraman Govindaraju
13d3f28f34 [Sparc] Add VIS instructions to sparc backend.
llvm-svn: 202660
2014-03-02 19:31:21 +00:00
Venkatraman Govindaraju
caf11daede [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
llvm-svn: 202628
2014-03-02 09:46:56 +00:00
Venkatraman Govindaraju
e478c48fa6 [Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.
llvm-svn: 202616
2014-03-02 06:28:15 +00:00
Venkatraman Govindaraju
6aea38dc6d [Sparc] Add support for parsing fcmp with %fcc registers.
llvm-svn: 202610
2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
1c2ec775cb [SparcV9] Add support for parsing branch instructions with prediction.
llvm-svn: 202602
2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju
44a4d4b894 [Sparc] Add support for parsing annulled branch instructions.
llvm-svn: 202599
2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju
30d1614f94 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.
llvm-svn: 202598
2014-03-01 18:54:52 +00:00
Venkatraman Govindaraju
96169e7898 [Sparc] Add missing ALU instruction patterns.
llvm-svn: 202597
2014-03-01 17:51:00 +00:00
Sasa Stankovic
e04070bf23 Add missing FileCheck in test command line.
llvm-svn: 202594
2014-03-01 16:14:29 +00:00
Venkatraman Govindaraju
9a36f7b46b [Sparc] Add support to decode unimp instruction.
llvm-svn: 202581
2014-03-01 09:28:18 +00:00
Venkatraman Govindaraju
043ff79772 [Sparc] Add support to decode negative simm13 operands in the sparc disassembler.
llvm-svn: 202578
2014-03-01 09:11:57 +00:00
Venkatraman Govindaraju
fcbe857272 [Sparc] Add support for decoding call instructions in the sparc disassembler.
llvm-svn: 202577
2014-03-01 08:30:58 +00:00
Venkatraman Govindaraju
1eb4e172be [Sparc] Add support to disassemble sparc memory instructions.
llvm-svn: 202575
2014-03-01 07:46:33 +00:00
Venkatraman Govindaraju
78e98664c7 Add support for parsing sun-style section flags in ELFAsmParser.
llvm-svn: 202573
2014-03-01 06:21:00 +00:00
Venkatraman Govindaraju
9242ded302 [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just filling with zeroes.
llvm-svn: 202572
2014-03-01 05:45:09 +00:00
Venkatraman Govindaraju
dd81a65959 [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.
llvm-svn: 202571
2014-03-01 05:07:21 +00:00
Venkatraman Govindaraju
789e2fd1b7 [Sparc] Add support for parsing directives in SparcAsmParser.
llvm-svn: 202564
2014-03-01 02:18:04 +00:00
Venkatraman Govindaraju
439a7d90a6 [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code.
llvm-svn: 202563
2014-03-01 01:04:26 +00:00
Zoran Jovanovic
ebb68d0712 Fixed encoding of SYSCALL microMIPS instruction.
llvm-svn: 202523
2014-02-28 18:17:08 +00:00
Zoran Jovanovic
d914bd8ae2 Revert revision 202518 because of wrong commit message.
llvm-svn: 202521
2014-02-28 18:14:16 +00:00
Zoran Jovanovic
43ca53260b Fix operand of SC instruction.
llvm-svn: 202518
2014-02-28 18:02:17 +00:00
Sasa Stankovic
b0018b8bdb [mips] Implement NaCl sandboxing of indirect jumps:
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer).
  * Add masking instructions before indirect jumps (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2847

llvm-svn: 202479
2014-02-28 10:00:38 +00:00
Alp Toker
f3e1a22860 Fix typos
llvm-svn: 202107
2014-02-25 04:21:15 +00:00
Saleem Abdulrasool
e129b591f0 Asm Parser: support .error directive
The .error directive is similar to .err in that it will halt assembly if it is
evaluated for assembly.  However, it permits a user supplied message to be
rendered.

llvm-svn: 201999
2014-02-23 23:02:23 +00:00
Saleem Abdulrasool
72c71c83fc AsmParser: support .ifeqs directive
The .ifeqs directive assembles the following code if the quoted string
parameters are equal.  The strings must be quoted using double quotes.

llvm-svn: 201998
2014-02-23 23:02:18 +00:00
Saleem Abdulrasool
05ca7814d9 ARM IAS: support .align without parameters
.align is handled specially on certain targets.  .align without any parameters
on ARM indicates a default alignment (4).  Handle the special case in the target
parser, but fall back to the generic parser for the normal version.

llvm-svn: 201988
2014-02-23 17:45:32 +00:00
Saleem Abdulrasool
d5860dd600 MCAsmParser: support .ifne
The .ifne directive assembles the following section of code if the argument
expression is non-zero.  Effectively, it is equivalent to if.

llvm-svn: 201986
2014-02-23 15:53:41 +00:00
Saleem Abdulrasool
17ad744c96 MCAsmParser: handle space properly for .ifc/.ifnc
If the strings are not quoted, the first string stops at the first comma, and
the second string stops at the end of the line.  Strings which contain
whitespace should be quoted.  Unquoted space is to be discarded.

llvm-svn: 201985
2014-02-23 15:53:36 +00:00
Saleem Abdulrasool
e868833740 MCAsmParser: add support for .err directive
The .err directive produces an error whenever it is assembled.  This can be
useful for preventing assembly when an unexpected condition occurs.

llvm-svn: 201984
2014-02-23 15:53:30 +00:00
Saleem Abdulrasool
39ff879a52 ARM IAS: support .short and .hword
This adds support for the .short and its alias .hword for adding literal values
into the object file.  This is similar to the .word directive, however, rather
than inserting a value of 4 bytes, adds a 2-byte value.

llvm-svn: 201968
2014-02-23 06:22:09 +00:00
Nico Rieck
f53974774a MC: Support COFF string tables larger than 10MB
Offsets past the range of single-slash encoding are encoded as base64,
padded to 6 characters, and prefixed with two slashes. This encoding is
undocumented but used by MSVC.

llvm-svn: 201940
2014-02-22 16:12:20 +00:00
Daniel Sanders
1f73ab934b [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.
Summary:
This removes the need to coerce UnknownABI to the default ABI (O32 for
MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser.

Clang has been updated to disable both possible default ABI's before enabling
the ABI it intends to use.

[*] N64 being the default for MIPS64 is not actually correct.
    However N32 is not fully implemented/tested yet.

Depends on: D2830

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2832
Differential Revision: http://llvm-reviews.chandlerc.com/D2846

llvm-svn: 201792
2014-02-20 14:58:19 +00:00
Benjamin Kramer
6492a4878f AsmParser: Disable Darwin-style macro argument expansion on non-darwin targets.
There is code in the wild that relies on $0 not being expanded.

llvm-svn: 201784
2014-02-20 13:36:32 +00:00
Elena Demikhovsky
af8e1ef280 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.

llvm-svn: 201757
2014-02-20 06:34:39 +00:00
Daniel Sanders
b0b9c3767b [mips] Add explicit N32 and N64 tests to nabi-regs.s test
llvm-svn: 201684
2014-02-19 15:30:54 +00:00
Craig Topper
de3c74571e Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
llvm-svn: 201649
2014-02-19 08:25:02 +00:00
Craig Topper
5b20c52fcc Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
llvm-svn: 201641
2014-02-19 05:34:21 +00:00
Saleem Abdulrasool
27ee2a5853 MCAsmParser: support required parameters
This enhances the macro parser to parse and handle parameter qualifications,
which is needed to support required formal parameters in macro definitions.  A
required parameter may not be defaulted (though providing a default value is
accepted with a warning).  This improves GAS compatibility.

Partially addresses PR9248.

llvm-svn: 201630
2014-02-19 03:00:29 +00:00
Kevin Enderby
0a635e7acf Fix the arm assembler so that this malformed instruction:
ldrd r6, r7 [r2, #15]
simply gives an error and does not triggers an assertion.

As Jim points out, the diagnostic is really strange here,
but fixing that would be more complicated. The missing
comma results in the parser expecting a construct like r2[2],
which is the vector index thing the error message is talking
about. That's not what the user intended, though, and there's
nothing else in the instruction that looks at all like a vector.
Yet more fallout from not having a real parser here and trying
to do context-free generic matching for addressing modes.

rdar://15097243

llvm-svn: 201531
2014-02-17 21:45:27 +00:00
Anders Waldenborg
81a09cf058 Add support for assigning to . in AsmParser.
This is implemented by handling assignments to the '.' pseudo symbol
as ".org" directives.

Differential Revision: http://llvm-reviews.chandlerc.com/D2625

llvm-svn: 201530
2014-02-17 20:48:32 +00:00