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Commit Graph

3152 Commits

Author SHA1 Message Date
Craig Topper
3e74ac0d93 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
llvm-svn: 201507
2014-02-17 10:03:43 +00:00
Saleem Abdulrasool
dc9bca333a MCAsmParser: add some mixed argument tests
Add some tests to explicitly validate handling of comma and non-comma separated
arguments.

llvm-svn: 201500
2014-02-17 00:40:22 +00:00
Saleem Abdulrasool
31abfcc09f MCAsmParser: better handling for named arguments
Until this point only macro definition with named parameters were parsed but the
names were ignored.  This adds support for using that information for named
parameter instantiation.

In order to support the full semantics of the keyword arguments, the arguments
are no longer lazily initialised since the keyword arguments can be specified
out of order and partially if they are defaulted.  Prepopulate the arguments
with the default value for any defaulted parameters, and then parse the
specified arguments.

This simplies some of the handling of the arguments in the inner loop since
empty arguments simply increment the parameter index and move on.

Note that keyword and positional arguments cannot be mixed.

llvm-svn: 201499
2014-02-17 00:40:17 +00:00
Nico Rieck
02b2fbee0d Fix broken CHECK lines
llvm-svn: 201479
2014-02-16 07:31:05 +00:00
Saleem Abdulrasool
1ab302ffd6 MCAsmParser: relax declaration parsing
The Linux kernel defines empty macros for compatibility with ARM UAL syntax.
The comma after the name is optional, and if present can be safely lexed.  This
improves compatibility with the GNU assembler.

llvm-svn: 201474
2014-02-16 04:56:31 +00:00
Saleem Abdulrasool
f0e7fa2121 ARM IAS: (partially) support .arch_extension directive
This adds a partial implementation of the .arch_extension directive to the
integrated ARM assembler.  There are a number of limitations to this
implementation arising from the target backend support rather than the
implementation itself.  Namely, iWMMXT (v1 and v2), Maverick, and XScale support
is not present in the ARM backend.  Currently, there is no check for A-class
only (needed for virt), and no ARMv6k detection (needed for os and sec).  The
remainder of the extensions are fully supported.

llvm-svn: 201471
2014-02-16 00:16:41 +00:00
Craig Topper
17b586d7c5 Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.
llvm-svn: 201463
2014-02-15 07:29:18 +00:00
Diego Novillo
eb4175295c Support DWARF discriminators in object streamer.
Summary:
This adds support for emitting DWARF path discriminator values in
the object streamer. It also changes the DWARF dumper to show
discriminator values in the line table output.

Reviewers: echristo

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2794

llvm-svn: 201427
2014-02-14 19:27:53 +00:00
Diego Novillo
9f753a3e86 Simplify checks in MC/AsmParser/directive_loc.s
llvm-svn: 201361
2014-02-13 20:16:42 +00:00
Diego Novillo
26a166f74b Fix generation of 'isa' and 'discriminator' keywords.
Summary:
There should be a space before each of these two keywords to avoid
generating invalid assembly files.

NOTE: I could not find an obvious maintainers in CODE_OWNERS.TXT, but
      this seems related to debug info.

Reviewers: echristo

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2791

llvm-svn: 201359
2014-02-13 20:05:03 +00:00
Jim Grosbach
de38e9caf1 Tidy up a bit. Formatting only.
llvm-svn: 201174
2014-02-11 20:48:41 +00:00
Jim Grosbach
c13fd8cf77 ARM: Thumb2 LDR(literal) can target SP.
Fix a slightly overzealous destination register restriction for the
'without .w' alias. Add some explicit testcases.

rdar://16033140

llvm-svn: 201173
2014-02-11 20:48:39 +00:00
Elena Demikhovsky
ac4dfca982 AVX-512: Optimized BUILD_VECTOR pattern;
fixed encoding of VEXTRACTPS instruction.

llvm-svn: 201134
2014-02-11 07:25:59 +00:00
Chad Rosier
a434e7ab2c [AArch64] Handle aliases of conditional branches without b.pred form.
llvm-svn: 201091
2014-02-10 15:43:11 +00:00
Matheus Almeida
a37a49cc06 [mips][msa] Add DLSA instruction.
llvm-svn: 201081
2014-02-10 12:05:17 +00:00
Craig Topper
5f3cd9c3a9 Recommit r201059 and r201060 with hopefully a fix for its original failure.
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.

llvm-svn: 201065
2014-02-10 06:55:41 +00:00
Benjamin Kramer
dd9c671cdc AsmParser: Parse (and ignore) nested .macro definitions.
This enables a slightly odd feature of gas. The macro is defined when
the outermost macro is instantiated.

PR18599

llvm-svn: 201045
2014-02-09 16:22:00 +00:00
Saleem Abdulrasool
832f6bfd62 ARM: change attribute tests to use parsed form
This makes the tests more readable by using the -arm-attributes decoding support
in llvm-readobj since that is now available.  Change the invocation commands to
be similar to other test and use a more precise triple (the tests only require
ARM EABI support).

llvm-svn: 201029
2014-02-08 23:17:02 +00:00
Renato Golin
9fd4f091dc Remove -arm-disable-ehabi option
llvm-svn: 200988
2014-02-07 20:12:49 +00:00
Sasa Stankovic
deee198fc2 Changed comment.
llvm-svn: 200969
2014-02-07 11:16:02 +00:00
Venkatraman Govindaraju
b3d477bcf8 [Sparc] Add support for parsing synthetic instruction 'mov'.
llvm-svn: 200965
2014-02-07 09:06:52 +00:00
Venkatraman Govindaraju
772dbc91ad [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
llvm-svn: 200963
2014-02-07 07:34:49 +00:00
Kevin Enderby
de9b7be909 Update the X86 assembler for .intel_syntax to accept
the << and >> bitwise operators.

rdar://15975725

llvm-svn: 200896
2014-02-06 01:21:15 +00:00
Logan Chien
0d1789c768 ARM: Resolve thumb_bl fixup in same MCFragment.
In Thumb1 mode, bl instruction might be selected for branches between
basic blocks in the function if the offset is greater than 2KB.
However, this might cause SEGV because the destination symbol
is not marked as thumb function and the execution mode will be reset
to ARM mode.

Since we are sure that these symbols are in the same data fragment, we
can simply resolve these local symbols, and don't emit any relocation
information for this bl instruction.

llvm-svn: 200842
2014-02-05 14:15:16 +00:00
Elena Demikhovsky
20652531de AVX-512: fixed a bug in EVEX encoding (the bug appeared after r200624)
llvm-svn: 200837
2014-02-05 13:03:01 +00:00
Petar Jovanovic
615b3679ca [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2592

llvm-svn: 200783
2014-02-04 18:41:57 +00:00
David Woodhouse
29e7c4248c MC: Fix .octa output for APInts with BitWidth > 128
llvm-svn: 200615
2014-02-01 16:52:33 +00:00
David Woodhouse
03ba7e20e4 MC: Add support for .octa
This is a minimal implementation which accepts only constants rather than
full expressions, but that should be perfectly sufficient for all known
users for now.

Patch from PaX Team <pageexec@freemail.hu>

llvm-svn: 200614
2014-02-01 16:20:59 +00:00
David Majnemer
7af1524404 Update a .fill test to use the updated semantics.
Something funny happened, this should've been part of r200606.

llvm-svn: 200607
2014-02-01 07:36:52 +00:00
David Majnemer
9b4ef71ec8 MC: Improve the .fill directive's compatibility with GAS
Per the GAS documentation, .fill should permit pattern widths that
aren't a power of two. While I was in the neighborhood, I added some
sanity checking. This change was motivated by a use of this construct
in the Linux Kernel.

llvm-svn: 200606
2014-02-01 07:19:38 +00:00
Rafael Espindola
7ed26bece7 Remove another hasRawTextSupport.
To remove this one simply move the end of file logic from the asm printer to
the target mc streamer.

This removes the last call to hasRawTextSupport from lib/Target.

llvm-svn: 200590
2014-01-31 23:10:26 +00:00
Matheus Almeida
489791e923 [mips][msa] Add insert.d instruction.
This instruction is only available on Mips64 cores that implement the MSA ASE.

llvm-svn: 200543
2014-01-31 13:31:20 +00:00
Craig Topper
c56f5e167f Move address override handling in X86MCCodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.
llvm-svn: 200516
2014-01-31 05:33:45 +00:00
David Woodhouse
10eb2a8985 [x86] Fix signed relocations for i64i32imm operands
These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32.
Kill the horrid and incomplete special case and FIXME in
EncodeInstruction() and set things up so it can infer the signedness
from the ImmType just like it can the size and whether it's PC-relative.

llvm-svn: 200495
2014-01-30 22:20:41 +00:00
Timur Iskhodzhanov
04f94cf108 Fix PR18381 - print a minimal diagnostic rather than assert on unresolved .secidx target
llvm-svn: 200490
2014-01-30 21:13:05 +00:00
Saleem Abdulrasool
14399e6e4b ARM IAS: support .object_arch
The .object_arch directive indicates an alternative architecture to be specified
in the object file.  The directive does *not* effect the enabled feature bits
for the object file generation.  This is particularly useful when the code
performs runtime detection and would like to indicate a lower architecture as
the requirements than the actual instructions used.

llvm-svn: 200451
2014-01-30 04:46:41 +00:00
Saleem Abdulrasool
911a8d4f8f ARM IAS: support .movsp
.movsp is an ARM unwinding directive that indicates to the unwinder that a
register contains an offset from the current stack pointer.  If the offset is
unspecified, it defaults to zero.

llvm-svn: 200449
2014-01-30 04:46:24 +00:00
Saleem Abdulrasool
89a237a2c6 ARM: suuport .tlsdescseq directive
This enhances the ARMAsmParser to handle .tlsdescseq directives.  This is a
slightly special relocation.  We must be able to generate them, but not consume
them in assembly.  The relocation is meant to assist the linker in generating a
TLS descriptor sequence.  The ELF target streamer is enhanced to append
additional fixups into the current segment and that is used to emit the new
R_ARM_TLS_DESCSEQ relocations.

llvm-svn: 200448
2014-01-30 04:02:47 +00:00
Saleem Abdulrasool
1777c48c91 ARM: support TLS descriptor relocations
Add support for tlsdesc relocations which are part of the ABI, marked as
experimental.  These relocations permit the linker to perform TLS reference
optimizations.

llvm-svn: 200447
2014-01-30 04:02:38 +00:00
Saleem Abdulrasool
cf36b84709 ARM: support tlscall relocations
This adds support for TLS CALL relocations.  TLS CALL relocations are used to
indicate to the linker to generate appropriate entries to resolve TLS references
via an appropriate function invocation (e.g. __tls_get_addr(PLT)).

In order to accomodate the linker relaxation of the TLS access model for the
references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete.
This requires that the partial inplace value is also incomplete (i.e. 0).  We
simply avoid the offset value calculation at the time of the fixup adjustment in
the ARM assembler backend.

llvm-svn: 200446
2014-01-30 04:02:31 +00:00
David Majnemer
c3f8d074b2 MC: Better management of macro arguments
The linux kernel makes uses of a GAS `feature' which substitutes nothing
for macro arguments which aren't specified.

Proper support for these kind of macro arguments necessitated a cleanup of
differences between `GAS' and `Darwin' dialect macro processing.

Differential Revision: http://llvm-reviews.chandlerc.com/D2634

llvm-svn: 200409
2014-01-29 18:57:46 +00:00
Matheus Almeida
67244395fb [mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores
that implement the MSA ASE.

llvm-svn: 200400
2014-01-29 15:12:02 +00:00
Matheus Almeida
3e07e293c7 [mips][msa] Add copy_{u,s}.d.
These instructions are only available on Mips64 cores
that implement the MSA ASE.

llvm-svn: 200398
2014-01-29 14:05:28 +00:00
Renato Golin
6ca0034624 Enable EHABI by default
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

llvm-svn: 200388
2014-01-29 11:50:56 +00:00
David Majnemer
b3046f7fc8 MC: Reorganize macro MC test along dialect lines
This commit seeks to do two things:
 - Run the surfeit of tests under the Darwin dialect.  This ends up
   affecting tests which assumed that spaces could deliminate arguments.
 - The GAS dialect tests should limit their surface area to things that
   could plausibly work under GAS. For example, Darwin style arguments
   have no business being in such a test.

llvm-svn: 200383
2014-01-29 09:18:43 +00:00
David Woodhouse
69762f7e1e Tests for mode switching
1. test that inlineasm works
2. test that relaxable instructions are re-encoded in the correct mode.

llvm-svn: 200351
2014-01-28 23:13:30 +00:00
Matheus Almeida
6447ece792 [mips] Fix ELF header flags.
As opposed to GCC/GAS the default ABI for Mips64 is n64.
Compatibility bit should be set if o32 ABI is used when targeting Mips64.

llvm-svn: 200332
2014-01-28 19:24:11 +00:00
Mark Seaborn
1b9cb5e4a2 ARM MC: Fix the initial DWARF CFI unwind info at the start of a function
This brings MC into line with GNU 'as' on ARM, and it brings the ARM
target into line with most other LLVM targets, which declare the
initial CFI state with addInitialFrameState().

Without this, functions generated with .cfi_startproc/endproc on ARM
will tend to cause GDB to abort with:
  gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule.

I've also tested this by comparing the output of "readelf -w" on the
object files produced by llvm-mc and gas when given the .s file added
here.

This change is part of addressing PR18636.

Differential Revision: http://llvm-reviews.chandlerc.com/D2597

llvm-svn: 200255
2014-01-27 22:38:14 +00:00
David Majnemer
68ba6d5a5b MC: Add support for .cfi_startproc simple
This commit allows LLVM MC to process .cfi_startproc directives when
they are followed by an additional `simple' identifier. This signals to
elide the emission of target specific CFI instructions that would
normally occur initially.

This fixes PR16587.

Differential Revision: http://llvm-reviews.chandlerc.com/D2624

llvm-svn: 200227
2014-01-27 17:20:25 +00:00
Saleem Abdulrasool
91bd110de4 MC: fix test locations/name
Placed the MC variant diagnostics in the wrong directory accidentally.  Move
them into their respective architecture specific directories.

llvm-svn: 200161
2014-01-26 22:55:02 +00:00
Saleem Abdulrasool
bad8eceeeb ARM: improve diagnostics for .word directive
If a complex expression was passed to the .word directive and the first part of
the directive failed to parse, a secondary diagnostic would be produced that
would clutter the error diagnostics.  Improve the diagnostics by consuming the
remainder of the statement.

llvm-svn: 200160
2014-01-26 22:29:50 +00:00
Saleem Abdulrasool
254ffbe584 AsmParser: improve diagnostics for invalid variants
An emitted diagnostic for an invalid relocation variant would place the caret on
the token following the relocation variant indicator or at the end of the line
if there was no following token.  This change corrects the placement of the
caret to point to the token.

llvm-svn: 200159
2014-01-26 22:29:43 +00:00
Rafael Espindola
39bfe463a9 Implement the missing bits corresponding to .mips_hack_elf_flags.
These were:
* noreorder handling on the target object streamer and asm parser.
* setting the initial flag bits based on the enabled features.
* setting the elf header flag for micromips

It is *really* depressing I am the one doing this instead of someone at
mips actually taking the time to understand the infrastructure.

llvm-svn: 200138
2014-01-26 06:57:13 +00:00
Rafael Espindola
9aa795f436 Move tests that just use llc from test/MC/Mips to test/MC/Codegen.
This is an expanded version of r200064.

llvm-svn: 200115
2014-01-26 04:08:47 +00:00
Venkatraman Govindaraju
61788f1428 [Sparc] Add support for sparc relocation types in ELF object file.
llvm-svn: 200112
2014-01-26 03:21:28 +00:00
Artyom Skrobov
f31472a27e Reverting r199886 (Prevent repetitive warnings for unrecognized processors and features)
llvm-svn: 200083
2014-01-25 16:56:18 +00:00
Rafael Espindola
010c30aa7a This reverts commit r200064 and r200051.
r200064 depends on r200051.

r200051 is broken: I tries to replace .mips_hack_elf_flags, which is a good
thing, but what it replaces it with is even worse.

The new emitMipsELFFlags it adds corresponds to no assembly directive, is not
marked as a hack and is not even printed to the .s file.

The patch also introduces more uses of hasRawTextSupport.

The correct way to remove .mips_hack_elf_flags is to have the mips target
streamer handle the default flags (and command line options). That way the
same code path is used for asm and obj. The streamer interface should *really*
correspond to what is printed in the .s file.

llvm-svn: 200078
2014-01-25 15:06:56 +00:00
Jack Carter
9f78b0c7de [Mips] Move 2 test cases from MC to CodeGen.
No code changes. Just reassignment of test case files.

llvm-svn: 200064
2014-01-25 02:14:14 +00:00
Jack Carter
49b0483ce0 [Mips] TargetStreamer ELF flag Support for default and commandline options.
This patch uses a common MipsTargetSteamer interface for both 
MipsAsmPrinter and MipsAsmParser for recording default and commandline
driven directives that affect ELF header flags.

It has been noted that the .ll tests affected by this patch belong in
test/Codegen/Mips. I will move them in a separate patch.

Also, a number of directives do not get expressed by AsmPrinter in the 
resultant .s assembly such as setting the correct ASI. I have noted this
in the tests and they will be addressed in later patches.

llvm-svn: 200051
2014-01-25 00:24:07 +00:00
Alp Toker
1c4b33e8e5 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Venkatraman Govindaraju
740a35b34e [Sparc] Correct quad register list in the asm parser.
Add test cases to check parsing of v9 double registers and their aliased quad registers.

llvm-svn: 199974
2014-01-24 05:24:01 +00:00
Kevin Enderby
59d3a472c7 Update the X86 assembler for .intel_syntax to produce an error for invalid base
registers in memory addresses that do not match the index register. As it does
for .att_syntax.

rdar://15887380

llvm-svn: 199948
2014-01-23 22:34:42 +00:00
Kevin Enderby
04aaab5ef5 Update the X86 assembler for .intel_syntax to produce an error for invalid
scale factors in memory addresses. As it does for .att_syntax.

It was producing:
Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133.

rdar://14967214

llvm-svn: 199942
2014-01-23 21:52:41 +00:00
Artyom Skrobov
6e789cecc9 Prevent repetitive warnings for unrecognized processors and features
llvm-svn: 199886
2014-01-23 11:31:38 +00:00
Jack Carter
710434d0c0 [Mips] TargetStreamer Support for .set mips16.
This patch updates .set mips16 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that the assembler uses for
both ELF and ASCII output for these directives.

llvm-svn: 199851
2014-01-22 23:08:42 +00:00
David Woodhouse
fa88b9de95 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
llvm-svn: 199809
2014-01-22 15:08:55 +00:00
David Woodhouse
b7c155c55a [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)
llvm-svn: 199808
2014-01-22 15:08:49 +00:00
David Woodhouse
39833d37a3 [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)
llvm-svn: 199807
2014-01-22 15:08:42 +00:00
David Woodhouse
4515fd303f ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
llvm-svn: 199806
2014-01-22 15:08:36 +00:00
David Woodhouse
02c50a95e8 [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)
llvm-svn: 199805
2014-01-22 15:08:27 +00:00
David Woodhouse
59ef208820 [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
llvm-svn: 199804
2014-01-22 15:08:21 +00:00
David Woodhouse
e01fc03be8 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
llvm-svn: 199803
2014-01-22 15:08:08 +00:00
David Majnemer
4537541170 Forgot to add testcase for r198590
llvm-svn: 199765
2014-01-21 20:39:11 +00:00
Saleem Abdulrasool
aae6a31cf3 tools: support decoding ARM EHABI opcodes in readobj
Add support to llvm-readobj to decode the actual opcodes.  The ARM EHABI opcodes
are a variable length instruction set that describe the operations required for
properly unwinding stack frames.

The primary motivation for this change is to ease the creation of tests for the
ARM EHABI object emission as well as the unwinding directive handling in the ARM
IAS.

Thanks to Logan Chien for an extra test case!

llvm-svn: 199708
2014-01-21 02:33:15 +00:00
Saleem Abdulrasool
d7349ac01d ARM IAS: add support for .unwind_raw directive
This implements the unwind_raw directive for the ARM IAS.  The unwind_raw
directive takes the form of a stack offset value followed by one or more bytes
representing the opcodes to be emitted.  The opcode emitted will interpreted as
if it were assembled by the opcode assembler via the standard unwinding
directives.

Thanks to Logan Chien for an extra test!

llvm-svn: 199707
2014-01-21 02:33:10 +00:00
Saleem Abdulrasool
4a5175ebb3 ARM IAS: support .personalityindex
The .personalityindex directive is equivalent to the .personality directive with
the ARM EABI personality with the specific index (0, 1, 2).  Both of these
directives indicate personality routines, so enhance the personality directive
handling to take into account personalityindex.

Bonus fix: flush the UnwindContext at the beginning of a new function.

Thanks to Logan Chien for additional tests!

llvm-svn: 199706
2014-01-21 02:33:02 +00:00
David Woodhouse
d30df6b04f [x86] Fix disassembly of MOV16ao16 et al.
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

llvm-svn: 199654
2014-01-20 12:02:53 +00:00
David Woodhouse
2992f8669c [x86] Fix 16-bit disassembly of JCXZ/JECXZ
llvm-svn: 199653
2014-01-20 12:02:48 +00:00
David Woodhouse
316c7ec362 [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSL
The disassembler has a special case for 'L' vs. 'W' in its heuristic for
checking for 32-bit and 16-bit equivalents. We could expand the heuristic,
but better just to be consistent in using the 'L' suffix.

llvm-svn: 199652
2014-01-20 12:02:44 +00:00
David Woodhouse
1ae3cd66f2 [x86] Fix disassembly of callw instruction
Not quite sure why this was marked isAsmParserOnly, but it means that the
disassembler can't see it either.

llvm-svn: 199651
2014-01-20 12:02:40 +00:00
David Woodhouse
40ce5ad1c0 [x86] Fix 16-bit handling of OpSize bit
When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.

llvm-svn: 199650
2014-01-20 12:02:35 +00:00
David Woodhouse
302d198064 [x86] Support i386-*-*-code16 triple for emitting 16-bit code
llvm-svn: 199648
2014-01-20 12:02:25 +00:00
Kai Nacke
b191003529 ARM: add tlsldo relocation
Add support for the symbol(tlsldo) relocation. This is required in order to 
solve PR18554.

Reviewed by R. Golin, A. Korobeynikov.

llvm-svn: 199644
2014-01-20 11:00:40 +00:00
Kevin Qin
a1ebedbe48 [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser.
For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be
printed as #0.0 instead of #0. To support the history codes using #0,
we consider to let asm parser accept both #0.0 and #0.

llvm-svn: 199621
2014-01-20 02:14:05 +00:00
Saleem Abdulrasool
b7bd80577f ARM ELF: ensure that the tag types are corrected
Ensure that the tag types are reflected on a replacement.  This is particularly
important for the compatibility tag which has multiple representations where the
last definition wins.

llvm-svn: 199577
2014-01-19 08:25:41 +00:00
Saleem Abdulrasool
c5281b558c ARM: update build attributes for ABI r2.09
Update names for the names as per the current ABI errata.  Mark deprecated tags
as such.

llvm-svn: 199576
2014-01-19 08:25:35 +00:00
Benjamin Kramer
1f0b6cda68 ARM: Let the assembler reject v5 instructions in v4 mode.
PR18524.

llvm-svn: 199559
2014-01-18 19:03:19 +00:00
Renato Golin
035f4db32b Add MLA alias for ARMv4 support.
Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

llvm-svn: 199491
2014-01-17 13:53:08 +00:00
Craig Topper
913806d6aa Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.
llvm-svn: 199477
2014-01-17 07:44:10 +00:00
Craig Topper
5f334ea607 Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.
llvm-svn: 199476
2014-01-17 07:37:39 +00:00
Craig Topper
ad05ca604d Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q'
llvm-svn: 199474
2014-01-17 07:25:39 +00:00
Amara Emerson
b634c3f6a8 Move the xscale build attribute test to the proper place and remove the old one.
The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s

llvm-svn: 199393
2014-01-16 15:11:54 +00:00
Craig Topper
f63b7bc430 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
David Peixotto
5d70ac3303 Fix parsing of .symver directive on ARM
ARM assembly syntax uses @ for a comment, execpt for the second
parameter of the .symver directive which requires @ as part of the
symbol name. This commit fixes the parsing of this directive by
adding a special case for ARM for this one argumnet.

To make the change we had to move the AllowAtInIdentifier variable
to the MCAsmLexer interface (from AsmLexer) and expose a setter for
the value.  The ELFAsmParser then toggles this value when parsing
the second argument to the .symver directive for a target that
uses @ as a comment symbol

llvm-svn: 199339
2014-01-15 22:40:02 +00:00
Kevin Enderby
86672ec557 Update the X86 assembler for .intel_syntax to accept
the | and & bitwise operators.

rdar://15570412

llvm-svn: 199323
2014-01-15 19:05:24 +00:00
Zoran Jovanovic
954752e8f5 LL and SC decoder method fix.
llvm-svn: 199316
2014-01-15 13:17:33 +00:00
Zoran Jovanovic
eccf116cca Added support for LWU microMIPS instruction.
llvm-svn: 199315
2014-01-15 13:01:18 +00:00
David Majnemer
c0087ca297 WinCOFF: Transform IR expressions featuring __ImageBase into image relative relocations
MSVC on x64 requires that we create image relative symbol
references to refer to RTTI data. Seeing as how there is no way to
explicitly make reference to a given relocation type in LLVM IR, pattern
match expressions of the form &foo - &__ImageBase.

Differential Revision: http://llvm-reviews.chandlerc.com/D2523

llvm-svn: 199312
2014-01-15 09:16:42 +00:00
Rafael Espindola
e6e64c63b4 Only mark functions as micromips.
The GNU as behavior is a bit different and very strange. It will mark any
label that contains an instruction. We can implement that, but using the
type looks more natural since gas will not mark a function if a .word is
used to output the instructions!

llvm-svn: 199287
2014-01-15 03:07:12 +00:00
Zoran Jovanovic
618c7b08b2 Test case micromips-load-effective-address.s renamed to micromips-load-effective-address.ll and moved to test/CodeGen/Mips.
llvm-svn: 199221
2014-01-14 16:26:47 +00:00