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Commit Graph

3152 Commits

Author SHA1 Message Date
Rafael Espindola
8113c62abe Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips".
This matches what gnu as does and implementing this is easier than arguing
about it.

llvm-svn: 199181
2014-01-14 04:25:13 +00:00
David Woodhouse
a7b8d3d331 [x86] Fix retq/retl handling in 64-bit mode
This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

llvm-svn: 199106
2014-01-13 14:05:59 +00:00
Saleem Abdulrasool
b90512a41c correct target directive handling error handling
The target specific parser should return `false' if the target AsmParser handles
the directive, and `true' if the generic parser should handle the directive.
Many of the target specific directive handlers would `return Error' which does
not follow these semantics.  This change simply changes the target specific
routines to conform to the semantis of the ParseDirective correctly.

Conformance to the semantics improves diagnostics emitted for the invalid
directives.  X86 is taken as a sample to ensure that multiple diagnostics are
not presented for a single error.

llvm-svn: 199068
2014-01-13 01:15:39 +00:00
Saleem Abdulrasool
c74b8ca814 ARM IAS: fix diagnostics of improper qualification
An improper qualifier would result in a superfluous error due to the parser not
consuming the remainder of the statement.  Simply consume the remainder of the
statement to avoid the error.

llvm-svn: 199035
2014-01-12 05:25:44 +00:00
Venkatraman Govindaraju
816c9a7dd9 [Sparc] Add support for parsing floating point instructions.
llvm-svn: 199033
2014-01-12 04:48:54 +00:00
Saleem Abdulrasool
1a40ebc0d6 ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

llvm-svn: 199032
2014-01-12 04:36:01 +00:00
Joerg Sonnenberger
8a42fa06ce Typo
llvm-svn: 199027
2014-01-12 03:38:30 +00:00
Joerg Sonnenberger
d23fb01819 Add missing mul aliases for armv4 support. Add checks that armv4 can
assemble the various mul instructions.

llvm-svn: 199026
2014-01-12 03:35:18 +00:00
Saleem Abdulrasool
2c235839b6 ARM IAS: support emitting constant values in target expressions
A 32-bit immediate value can be formed from a constant expression and loaded
into a register.  Add support to emit this into an object file.  Because this
value is a constant, a relocation must *not* be produced for it.

llvm-svn: 199023
2014-01-11 23:03:48 +00:00
Artyom Skrobov
cbb9547cdc Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M
llvm-svn: 198946
2014-01-10 16:49:49 +00:00
Artyom Skrobov
759f6384e9 Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
llvm-svn: 198945
2014-01-10 16:42:55 +00:00
Saleem Abdulrasool
f544263238 ARM: fix regression caused by r198914
The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

llvm-svn: 198944
2014-01-10 16:22:47 +00:00
Saleem Abdulrasool
4af9bf355f ARM IAS: support #:{lower,upper}16: for GNU compatibility
The GNU assembler supports prefixing the expression with a '#' to indiciate that
the value that is being moved is infact a constant.  This improves the
compatibility of the integrated assembler's parser for this.

llvm-svn: 198916
2014-01-10 04:38:40 +00:00
Saleem Abdulrasool
54cac13cc3 ARM IAS: support GNU extension for ldrd, strd
The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

llvm-svn: 198915
2014-01-10 04:38:35 +00:00
Saleem Abdulrasool
b7a097a617 ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

llvm-svn: 198914
2014-01-10 04:38:31 +00:00
Venkatraman Govindaraju
c4cec3f2a4 [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.
llvm-svn: 198909
2014-01-10 01:48:17 +00:00
Kevin Enderby
5c3b5e0470 Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions that
branch to the next instruction.  This can not be encoded but can be
turned into a NOP.

rdar://15062072

llvm-svn: 198904
2014-01-10 00:43:32 +00:00
Ana Pazos
0dec95c1c6 [AArch64][NEON] Added UXTL and UXTL2 instruction aliases
llvm-svn: 198791
2014-01-08 21:02:13 +00:00
Roman Divacky
9305a7c022 Force emit a relocation for @gnu_indirect_function symbols so that the indirect
resolution works.

llvm-svn: 198780
2014-01-08 18:50:32 +00:00
David Woodhouse
444fbac42d [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8
llvm-svn: 198763
2014-01-08 12:58:40 +00:00
David Woodhouse
5c8e725a8c [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)
They do *different* things to %esp, so they are not equivalent.

Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8.

llvm-svn: 198761
2014-01-08 12:58:32 +00:00
David Woodhouse
9dac8e32ee [x86] Make AsmParser validate registers for memory operands a bit better
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

llvm-svn: 198760
2014-01-08 12:58:28 +00:00
David Woodhouse
399c563e5e [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
2014-01-08 12:58:24 +00:00
David Woodhouse
b095fceafc [x86] Use 16-bit addressing where possible in 16-bit mode
Where "where possible" means that it's an immediate value and it's below
0x10000. In fact GAS will either truncate or error with larger values,
and will insist on using the addr32 prefix to get 32-bit addressing. So
perhaps we should do that, in a later patch.

llvm-svn: 198758
2014-01-08 12:58:18 +00:00
David Woodhouse
4e810363d9 [x86] Fix JCXZ,JECXZ_32 for 16-bit mode
JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.

llvm-svn: 198757
2014-01-08 12:58:12 +00:00
David Woodhouse
e757b998ec [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode
I couldn't see how to do this sanely without splitting RETQ from RETL.

Eric says: "sad about the inability to roundtrip them now, but...".
I have no idea what that means, but perhaps it wants preserving in the
commit comment.

llvm-svn: 198756
2014-01-08 12:58:07 +00:00
David Woodhouse
7d0744dadf [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
llvm-svn: 198755
2014-01-08 12:57:55 +00:00
David Woodhouse
38e7bff9f3 [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases
llvm-svn: 198754
2014-01-08 12:57:49 +00:00
David Woodhouse
9c25ab3643 [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode
llvm-svn: 198753
2014-01-08 12:57:45 +00:00
David Woodhouse
8bc826fd14 [x86] Add OpSize16 to instructions that need it
This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

llvm-svn: 198752
2014-01-08 12:57:40 +00:00
Venkatraman Govindaraju
0e7023f897 [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
llvm-svn: 198740
2014-01-08 07:47:57 +00:00
Venkatraman Govindaraju
d26e61b5c9 [Sparc] Add support for parsing branch instructions and conditional moves.
llvm-svn: 198738
2014-01-08 06:14:52 +00:00
Saleem Abdulrasool
3374bbd05c ARM IAS: properly handle expression operands
Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

llvm-svn: 198735
2014-01-08 03:28:14 +00:00
Roman Divacky
5894163dfa In the ELFWriter when writing aliased (.set) symbols dont blindly
take type from the new symbol but merge them so that the type
is never "downgraded".

This is probably quite rare, except for IFUNC symbols which
we used to misassemble, losing the IFUNC type.

Fixes #18372.

llvm-svn: 198706
2014-01-07 20:17:03 +00:00
David Peixotto
6a38357783 Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64
This commit adds the pre-UAL aliases of fconsts and fconstd for
vmov.f32 and vmov.f64. They use an InstAlias rather than a
MnemonicAlias to properly support the predicate operand.

We need to support encoded 8-bit constants in order to implement the
pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this
commit also fixes parsing of encoded floating point constants used
in vmov.f32/vmov.f64 instructions. Now we can support assembly code
like this:

  fconsts s0, #0x70

which is equivalent to vmov.f32 s0, #1.0.

Most of the code was already in place to support this feature.
Previously the code was trying to accept encoded 8-bit float
constants for the vmov.f32/vmov.f64 instructions.  It looks like the
support for parsing encoded floats was lost in a refactoring in
commit r148556 and we did not have any tests in place to catch it.

The change in this commit is to keep the parsed value as a 32-bit
float instead of a 64-bit double because that is what the isFPImm()
function expects to find. There is no loss of precision by using a
32-bit float here because we are still limited to an 8-bit encoded
value in the end.

Additionally, we explicitly reject encoded 8-bit floats for
vmovf.32/64. This is the same as the current behavior, but we now do
it explicitly rather than accidently.

llvm-svn: 198697
2014-01-07 18:19:23 +00:00
Venkatraman Govindaraju
69760d5a12 [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc.,
Also, correct the offsets for FixupsKindInfo.

llvm-svn: 198681
2014-01-07 08:00:49 +00:00
Saleem Abdulrasool
90329d7060 ARM IAS: allow more depth in contextual diagnostics
Switch the context to be SmallVectors.  This allows for saving additional
context when providing previous emission sites.

llvm-svn: 198665
2014-01-07 02:29:00 +00:00
Saleem Abdulrasool
58df683088 ARM IAS: refactor unwind context
Move the unwinding context for the ARM IAS into a helper class.  This is purely
a structural refactoring.  A follow up change allows for recording additional
depth to improve diagnostics.

llvm-svn: 198664
2014-01-07 02:28:55 +00:00
Saleem Abdulrasool
9005119e13 ARM IAS: improve .eabi_attribute handling
Parse tag names as well as expressions.  The former is part of the
specification, the latter is for improved compatibility with the GNU assembler.
Fix attribute value handling to be comformant to the specification.

llvm-svn: 198662
2014-01-07 02:28:42 +00:00
Saleem Abdulrasool
3d4218e538 MCParser: introduce Note and use it for ARM AsmParser
Introduce a new virtual method Note into the AsmParser.  This completements the
existing Warning and Error methods.  Use the new method to clean up the output
of the unwind routines in the ARM AsmParser.

llvm-svn: 198661
2014-01-07 02:28:31 +00:00
Venkatraman Govindaraju
a9c093fcc8 [Sparc] Add support for parsing memory operands in sparc AsmParser.
llvm-svn: 198658
2014-01-07 01:49:11 +00:00
Jack Carter
4a5987eef3 [Mips] TargetStreamer Support for .abicalls and .set pic0.
This patch adds .abicalls and .set pic0 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that both the integrated and standalone
assemblers will use for the output for these directives.

llvm-svn: 198646
2014-01-06 23:27:31 +00:00
Venkatraman Govindaraju
63a6ceb84a [Sparc] Add initial implementation of disassembler for sparc
llvm-svn: 198591
2014-01-06 08:08:58 +00:00
Craig Topper
79635848a9 Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit mode
The 0x66 prefix toggles between 16-bit and 32-bit addressing mode.
So in 32-bit mode it is used to switch to 16-bit addressing mode for the
following instruction, while in 16-bit mode it's the other way round — it's
used to switch to 32-bit mode instead.

Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode,
and introduce a new OpSize16 bit which is used in 16-bit mode instead.

This is just the basic infrastructure for that change; a subsequent patch
will add the new OpSize16 bit to the 32-bit instructions that need it.

Patch from David Woodhouse.

llvm-svn: 198586
2014-01-06 06:02:58 +00:00
Craig Topper
201bd5add3 [x86] Add basic support for .code16
This is not really expected to work right yet. Mostly because we will
still emit the OpSize (0x66) prefix in all the wrong places, along with
a number of other corner cases. Those will all be fixed in the subsequent
commits.

Patch from David Woodhouse.

llvm-svn: 198584
2014-01-06 04:55:54 +00:00
Craig Topper
71734d085a Fix ModR/M byte output for 16-bit addressing modes (PR18220)
Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.

llvm-svn: 198566
2014-01-05 19:40:56 +00:00
Venkatraman Govindaraju
77e789f69a Add lit.local.cfg for MC/Sparc
llvm-svn: 198536
2014-01-05 03:07:04 +00:00
Venkatraman Govindaraju
7b675d45b0 [Sparc] Add initial implementation of MC Code emitter for sparc.
llvm-svn: 198533
2014-01-05 02:13:48 +00:00
Craig Topper
83505ed565 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
llvm-svn: 198530
2014-01-05 01:35:51 +00:00
Ana Pazos
2ad0c92db1 [AArch64][NEON] Added SXTL and SXTL2 instruction aliases
llvm-svn: 198437
2014-01-03 19:20:31 +00:00
Logan Chien
afb46ba663 [arm] Add softvfp to supported FPU names.
llvm-svn: 198313
2014-01-02 15:50:02 +00:00
Craig Topper
9d2e15270b Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
llvm-svn: 198278
2014-01-01 15:29:32 +00:00
Craig Topper
c39353ad9b Add two fp test cases I missed in my previous commit.
llvm-svn: 198269
2013-12-31 23:15:19 +00:00
Craig Topper
37d0ec7d41 Add more X86 FP stack disassembler test cases.
llvm-svn: 198268
2013-12-31 22:51:53 +00:00
Craig Topper
d0374cb642 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
llvm-svn: 198265
2013-12-31 17:21:44 +00:00
Saleem Abdulrasool
b3b5b0ab09 ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235
2013-12-30 18:38:01 +00:00
Saleem Abdulrasool
6f98f56dff ARM: provide VFP aliases for pre-V6 mnemonics
In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172
2013-12-29 17:58:35 +00:00
Saleem Abdulrasool
e4373d751b AsmParser: cleanup diagnostics for .rep/.rept
Avoid double diagnostics for invalid expressions for count.  Improve caret
location for negative count.

llvm-svn: 198099
2013-12-28 06:39:29 +00:00
Saleem Abdulrasool
11a48b8359 IAS: support .rep as an alias for .rept
The GNU assembler supports .rep as an alias for .rept.  This simply creates the
alias for it and introduces a test for both .rept and .rep.

llvm-svn: 198097
2013-12-28 05:54:33 +00:00
Joerg Sonnenberger
e549217adc Recognize armv7a and friends as aliases for armv7-a etc. for the purpose
of architecture naming.

llvm-svn: 198043
2013-12-26 11:50:28 +00:00
Saleem Abdulrasool
d63e2f47bf ARM IAS: support .even directive
The .even directive aligns content to an evan-numbered address.  This is an ARM
specific directive applicable to any section.

llvm-svn: 198031
2013-12-26 01:52:28 +00:00
Elena Demikhovsky
e1e562fcd2 AVX-512: decoder for AVX-512, made by Alexey Bader.
llvm-svn: 198013
2013-12-25 11:40:51 +00:00
Zoran Jovanovic
f9d8ca7036 Support for microMIPS load effective address.
llvm-svn: 198010
2013-12-25 10:14:07 +00:00
Zoran Jovanovic
427d20b793 Support for microMIPS FPU instructions 2.
llvm-svn: 198009
2013-12-25 10:09:27 +00:00
Richard Sandiford
54c1801ee8 [SystemZ] Add MC support for interlocked-access 1 instructions
llvm-svn: 197984
2013-12-24 15:14:05 +00:00
Saleem Abdulrasool
b26620d3fc ARM: bkpt has an implicit immediate constant 0
The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise
specified.  Add an instruction alias for the unvalued breakpoint mnemonic to
treat it as a 0.  This improves compatibility with GNU AS.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 197913
2013-12-23 17:23:58 +00:00
Timur Iskhodzhanov
04d669c011 Add the .secidx test I've forgotten to svn add in 197826
llvm-svn: 197828
2013-12-20 19:06:50 +00:00
Zoran Jovanovic
b55909330e Support for microMIPS FPU instructions 1.
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
Saleem Abdulrasool
e75f7af412 ARM IAS: add support for the .pool directive
The .pool directive is an alias for the .ltorg directive used to create a
literal pool.  Simply treat .pool as if .ltorg was passed.

llvm-svn: 197787
2013-12-20 07:21:16 +00:00
Kevin Enderby
b0799fc34d Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me with
this commit as the only one on the Blamelist so I quickly reverted this.
However it was actually Nick's change who has since fixed that issue.

Original commit message:

Changed the X86 assembler for intel syntax to work with directional labels.

The X86 assembler as a separate code to parser the intel assembly syntax
in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
And if something like 1f was used as a branch target it would get an
"Unexpected token" error.

The fix starts in X86AsmParser::ParseIntelExpression() in the case for
AsmToken::Integer, it needs to grab the IntVal from the current token
then look for a 'b' or 'f' following an Integer.  Then it basically needs to
do what is done in AsmParser::parsePrimaryExpr() for directional
labels.  It saves the MCExpr it creates in the IntelExprStateMachine
in the Sym field.

When it returns to X86AsmParser::ParseIntelOperand() it looks
for a non-zero Sym field in the IntelExprStateMachine and if
set it creates a memory operand not an immediate operand
it would normally do for the Integer.

rdar://14961158

llvm-svn: 197744
2013-12-19 23:16:14 +00:00
Kevin Enderby
63d4a91601 Revert my change to the X86 assembler for intel syntax to work with
directional labels.  Because it doesn't work for windows :)

llvm-svn: 197731
2013-12-19 22:24:09 +00:00
Kevin Enderby
aaa32c63ce Changed the X86 assembler for intel syntax to work with directional labels.
The X86 assembler has a separate code to parser the intel assembly syntax
in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
And if something like 1f was used as a branch target it would get an
"Unexpected token" error.

The fix starts in X86AsmParser::ParseIntelExpression() in the case for
AsmToken::Integer, it needs to grab the IntVal from the current token
then look for a 'b' or 'f' following the Integer.  Then it basically needs to
do what is done in AsmParser::parsePrimaryExpr() for directional
labels.  It saves the MCExpr it creates in the IntelExprStateMachine
in the Sym field.

When it returns to X86AsmParser::ParseIntelOperand() it looks
for a non-zero Sym field in the IntelExprStateMachine and if
set it creates a memory operand not an immediate operand
it would normally do for the Integer.

rdar://14961158

llvm-svn: 197728
2013-12-19 22:02:03 +00:00
David Peixotto
16536db0ae Implement the .ltorg directive for ARM assembly
This directive will write out the assembler-maintained constant
pool for the current section. These constant pools are created to
support the ldr-pseudo instruction (e.g. ldr r0, =val).

The directive can be used by the programmer to place the constant
pool in a location that can be reached by a pc-relative offset in
the ldr instruction.

llvm-svn: 197711
2013-12-19 18:26:07 +00:00
David Peixotto
a66e68bb52 Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,

  ldr r0, =0x10001
  ldr r1, =bar

will generate this output in the final assembly

  ldr r0, .Ltmp0
  ldr r1, .Ltmp1
  ...
  .Ltmp0: .long 0x10001
  .Ltmp1: .long bar

Sketch of the LDR pseudo implementation:
  Keep a map from Section => ConstantPool

  When parsing ldr r0, =val
    parse val as an MCExpr
    get ConstantPool for current Section
    Label = CreateTempSymbol()
    remember val in ConstantPool at next free slot
    add operand to ldr that is MCSymbolRef of Label

  On finishParse() callback
    Write out all non-empty constant pools
    for each Entry in ConstantPool
      Emit Entry.Label
      Emit Entry.Value

Possible improvements to be added in a later patch:
  1. Does not convert load of small constants to mov
     (e.g. ldr r0, =0x1 => mov r0, 0x1)
  2. Does reuse constant pool entries for same constant

The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.

llvm-svn: 197708
2013-12-19 18:12:36 +00:00
Zoran Jovanovic
e6baed485f Support for microMIPS control instructions.
llvm-svn: 197696
2013-12-19 16:25:00 +00:00
Hal Finkel
ce61543897 Add a disassembler to the PowerPC backend
The tests for the disassembler were adapted from the encoder tests, and for the
most part, the output from the disassembler matches that encoder-test inputs.
There are some places where more-informative mnemonics could be produced
(notably for the branch instructions), and those cases are noted in the tests
with FIXMEs.

Future work includes:

 - Generating more-informative mnemonics when possible (this may also be done
   in the printer).

 - Remove the dependence on positional "numbered" operand-to-variable mapping
   (for both encoding and decoding).

 - Internally using 64-bit instruction variants in 64-bit mode (if this turns
   out to matter).

llvm-svn: 197693
2013-12-19 16:13:01 +00:00
Zoran Jovanovic
a4d6da998d Support for microMIPS LL and SC instructions.
llvm-svn: 197692
2013-12-19 16:12:56 +00:00
Zoran Jovanovic
6b16ca6dfa Support for microMIPS TLS relocations.
llvm-svn: 197685
2013-12-19 16:02:32 +00:00
Saleem Abdulrasool
a48f1a5b54 ARM IAS: support .inst directive
This adds support for the .inst directive.  This is an ARM specific directive to
indicate an instruction encoded as a constant expression.  The major difference
between .word, .short, or .byte and .inst is that the latter will be
disassembled as an instruction since it does not get flagged as data.

llvm-svn: 197657
2013-12-19 05:17:58 +00:00
Matheus Almeida
351a06901f [mips][msa] Update format of RUN lines for every MSA MC test.
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.

llvm-svn: 197588
2013-12-18 17:31:21 +00:00
Matheus Almeida
25c76494df [mips][msa] Remove unneeded triple directive in MSA MC tests.
No functional changes.

llvm-svn: 197559
2013-12-18 11:06:13 +00:00
Saleem Abdulrasool
58e7056c0b AsmParser: add support for .end directive
The .end directive indicates the end of the file.  No further instructions are
processed after a .end directive is encountered.

One potential (glaringly obvious) optimisation that could be pursued here is to
extend MCAsmParser with a DiscardRemainder method to avoid processing lexemes to
the end of the file.  It was unclear at this point if that would be worth
adding, and could easily be added in a follow on change.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 197547
2013-12-18 02:53:03 +00:00
Reid Kleckner
7f077ea70a MC COFF: Emit the 'b' section flag for .bss sections in GNU assembly
Without this, assembling clang's disassembly would produce an object
file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic
rather than the uninitialized one.  link.exe would warn when merging
comdats with different flags.

llvm-svn: 197529
2013-12-17 22:12:40 +00:00
Matheus Almeida
b7efcc666c [mips] Fix off by one issue when applying a fixup.
The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.

llvm-svn: 197506
2013-12-17 17:10:00 +00:00
Kevin Enderby
e6ab982310 Fixed a bug in getARMFixupKindMachOInfo() where three ARM fixup kinds
were falling into the cases for 24-bit branch kinds which are not 24-bit
branches.  The routine is to return false for fixups are expected to always
be resolvable at assembly time. Which these three fixups are as they have
limited displacement and are for local references within a function.

rdar://15586725

llvm-svn: 197282
2013-12-13 22:46:54 +00:00
Andrew Trick
e726cc0278 Grow the stackmap/patchpoint format to hold 64-bit IDs.
llvm-svn: 197255
2013-12-13 18:37:10 +00:00
Matheus Almeida
b273b4d798 [mips] Add checks for alignment and maximum displacements for most of the
branch instructions for mips and micromips instruction sets thus avoiding
the situation of generating branches to undesired locations if offsets
cannot be encoded.

This patch also checks if a fixup cannot be applied and returns a fatal error
if that's the case.

llvm-svn: 197223
2013-12-13 11:11:02 +00:00
Logan Chien
50a059d70f [arm] Pass -triple to llvm-mc for ARM ELF test cases.
Replace -arch with -triple so that we can guarantee that
ELF object files can be generated.

llvm-svn: 197062
2013-12-11 19:38:10 +00:00
Logan Chien
e6b3d37d36 [arm] Implement ARM .arch directive.
llvm-svn: 197052
2013-12-11 17:16:25 +00:00
Vladimir Medic
4d40c9969e Method parseSetAssignment treats every operand with '$' sign as register and the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps)
As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example:
   .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names.

llvm-svn: 196773
2013-12-09 11:03:25 +00:00
David Peixotto
ff3935d81d Integrated assembler incorrectly lexes ARM-style comments
The integrated assembler fails to properly lex arm comments when
they are adjacent to an identifier in the input stream. The reason
is that the arm comment symbol '@' is also used as symbol variant in
other assembly languages so when lexing an identifier it allows the
'@' symbol as part of the identifier.

Example:
  $ cat comment.s
  foo:
    add r0, r0@got to parse this as a comment

  $ llvm-mc -triple armv7 comment.s
  comment.s:4:18: error: unexpected token in argument list
    add r0, r0@got to parse this as a comment
                   ^
This should be parsed as correctly as `add r0, r0`.

This commit modifes the assembly lexer to not include the '@' symbol
in identifiers when lexing for targets that use '@' for comments.

llvm-svn: 196607
2013-12-06 20:35:58 +00:00
Matheus Almeida
f0fc3cf095 [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
2013-12-05 11:06:22 +00:00
Alp Toker
e845f8af67 Correct word hyphenations
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

llvm-svn: 196471
2013-12-05 05:44:44 +00:00
NAKAMURA Takumi
44a125b7f6 Move llvm/test/MC/ELF/thumb-st_other.s to test/MC/ARM.
llvm-svn: 196457
2013-12-05 02:21:44 +00:00
Logan Chien
558333e1e1 [mc] Fix ELF st_other flag.
ELF_Other_Weakref and ELF_Other_ThumbFunc seems to be LLVM
internal ELF symbol flags.  These should not be emitted to
object file.

This commit defines ELF_STO_Shift for the target-defined
flags for st_other, and increase the value of
ELF_Other_Shift to 16.

llvm-svn: 196440
2013-12-05 00:34:11 +00:00
Kevin Enderby
218f72b95b Fix a bug in darwin's 32-bit X86 handling of evaluating fixups.
Where it would use a scattered relocation entry but falls back to a
normal relocation entry because the FixupOffset is more than 24-bits.

The bug is in the X86MachObjectWriter::RecordScatteredRelocation() where
it changes reference parameter FixedValue but then returns false to indicate
it did not create a scattered relocation entry.  The fix is simply to save the
original value of the parameter FixedValue at the start of the method and
restore it if we are returning false in that case.

rdar://15526046

llvm-svn: 196432
2013-12-04 23:36:24 +00:00
David Peixotto
b6710ff7c7 Add support for parsing ARM symbol variants on ELF targets
ARM symbol variants are written with parens instead of @ like this:

  .word __GLOBAL_I_a(target1)

This commit adds support for parsing these symbol variants in
expressions. We introduce a new flag to MCAsmInfo that indicates the
parser should use parens to parse the symbol variant. The expression
parser is modified to look for symbol variants using parens instead
of @ when the corresponding MCAsmInfo flag is true.

The MCAsmInfo parens flag is enabled only for ARM on ELF.

By adding this flag to MCAsmInfo, we are able to get rid of
redundant ARM-specific symbol variants and use the generic variants
instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new
UseParensForSymbolVariant attribute in MCAsmInfo to correctly print
the symbol variants for arm.

To achive this we need to keep a handle to the MCAsmInfo in the
MCSymbolRefExpr class that we can check when printing the symbol
variant.

Updated Tests:
  Changed case of symbol variant to match the generic kind.
  test/CodeGen/ARM/tls-models.ll
  test/CodeGen/ARM/tls1.ll
  test/CodeGen/ARM/tls2.ll
  test/CodeGen/Thumb2/tls1.ll
  test/CodeGen/Thumb2/tls2.ll

PR18080

llvm-svn: 196424
2013-12-04 22:43:20 +00:00
Rafael Espindola
f394b917ee Produce deterministic coff files.
llvm-svn: 196341
2013-12-04 02:02:55 +00:00
Juergen Ributzka
8504aa2736 [Stackmap] Specify the triple and cpu to fix the unit test.
llvm-svn: 196339
2013-12-04 01:02:37 +00:00
Juergen Ributzka
f7f5626671 [Stackmap] Emit multi-byte nops for X86.
llvm-svn: 196334
2013-12-04 00:39:08 +00:00
Rafael Espindola
5b33cec985 Output .eh_frames on COFF too now that the integrated as is used on mingw.
llvm-svn: 196104
2013-12-02 14:59:34 +00:00
Zoran Jovanovic
335dc8689e Test case for issue with microMIPS long branch.
llvm-svn: 195976
2013-11-30 19:13:15 +00:00
Zoran Jovanovic
b8cffe14c6 Revert revision 195965.
llvm-svn: 195967
2013-11-29 22:10:02 +00:00
Zoran Jovanovic
797919cb22 Fixed issue with microMIPS long branch.
llvm-svn: 195965
2013-11-29 21:41:24 +00:00
Kevin Qin
b95721d200 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
llvm-svn: 195936
2013-11-29 01:29:16 +00:00
Hao Liu
2f617213ef AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
llvm-svn: 195903
2013-11-28 01:07:45 +00:00
Rafael Espindola
c099bf8035 Use the same tls section name as msvc.
We currently error in clang with:
"error: thread-local storage is unsupported for the current target", but we
can start to get the llvm level ready.

When compiling

template<typename T>
struct foo {
  static __declspec(thread) int bar;
};
template<typename T>
__declspec(therad) int foo<T>::bar;
template struct foo<int>;

msvc produces

SECTION HEADER #3
   .tls$ name
       0 physical address
       0 virtual address
       4 size of raw data
     12F file pointer to raw data (0000012F to 00000132)
       0 file pointer to relocation table
       0 file pointer to line numbers
       0 number of relocations
       0 number of line numbers
C0301040 flags
         Initialized Data
         COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA)
         4 byte align
         Read Write

gcc produces a ".data$__emutls_v.<symbol>" for the testcase with
__declspec(thread) replaced with thread_local.

llvm-svn: 195849
2013-11-27 15:52:11 +00:00
Chad Rosier
ca062e81db [AArch64] Add support for NEON scalar floating-point absolute difference.
llvm-svn: 195803
2013-11-27 01:45:58 +00:00
Rafael Espindola
3ceb67b21b Use simple section names for COMDAT sections on COFF.
With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.

When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.

This survived a bootstrap on mingw32.

llvm-svn: 195798
2013-11-27 01:18:37 +00:00
Chad Rosier
1337fcc721 [AArch64] Add support for NEON scalar floating-point to integer convert
instructions.

llvm-svn: 195788
2013-11-26 22:17:37 +00:00
Rafael Espindola
ae17ac667e Use -triple to fix the test on non-ELF hosts.
llvm-svn: 195682
2013-11-25 20:46:18 +00:00
Rafael Espindola
fa5cbd5557 Don't use nopl in cpus that don't support it.
Patch by Mikulas Patocka. I added the test. I checked that for cpu names that
gas knows about, it also doesn't generate nopl.

The modified cpus:
i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta
        Crusoe, Microsoft VirtualBox - see
        https://bbs.archlinux.org/viewtopic.php?pid=775414
k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs
via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that
        Via c3 and c3-Nehemiah don't have nopl

llvm-svn: 195679
2013-11-25 20:15:14 +00:00
David Peixotto
647697e4ae ARM integrated assembler generates incorrect nop opcode
This patch fixes a bug in the assembler that was causing bad code to
be emitted.  When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.

Consider this small example:

$ cat align.s
.code 16
foo:
  add r0, r0
.align 3
  add r0, r0

$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
       0:       00 44         add     r0, r0
       2:       00 f0 20 e3   blx #4195904
       6:       00 00         movs    r0, r0
       8:       00 44         add     r0, r0

This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.

The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.

There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.

PR18019

llvm-svn: 195677
2013-11-25 19:11:13 +00:00
Rafael Espindola
a355ffef1b Fix .comm and .lcomm on COFF.
These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for
.comm.

Given

static int a;
int b;

MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With
this change we agree with gas on .lcomm, are much closer on .comm and clang-cl
matches msvc on the above example.

llvm-svn: 195654
2013-11-25 16:06:04 +00:00
Hao Liu
66ab312f94 Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

llvm-svn: 195591
2013-11-25 01:53:26 +00:00
Ana Pazos
86d72bbede Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.

llvm-svn: 195330
2013-11-21 08:16:15 +00:00
Jack Carter
6943b6e5c6 reverts 195057 per request
llvm-svn: 195152
2013-11-19 20:53:28 +00:00
Rafael Espindola
5d21406399 Support multiple COFF sections with the same name but different COMDAT.
This is the first step to fix pr17918.

It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given

.section foo
.linkonce....

.section foo
.linkonce

we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.

llvm-svn: 195148
2013-11-19 19:52:52 +00:00
Hao Liu
b26dfe0306 Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
llvm-svn: 195078
2013-11-19 02:17:05 +00:00
Kevin Qin
7b74269765 implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
llvm-svn: 195072
2013-11-19 01:40:25 +00:00
Jiangning Liu
7c858f236d Add predicate for AArch64 crypto instructions.
llvm-svn: 195071
2013-11-19 01:38:31 +00:00
Jack Carter
8bb31d387d [Mips] Support for MicroMips STO refactoring.
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.

llvm-svn: 195067
2013-11-19 01:25:18 +00:00
Reid Kleckner
552118c34a Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

llvm-svn: 195053
2013-11-18 23:08:12 +00:00
Matheus Almeida
a941fd6ccd [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.

llvm-svn: 195006
2013-11-18 13:09:54 +00:00
Matheus Almeida
f3405464c6 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.

llvm-svn: 195004
2013-11-18 12:32:49 +00:00
Kevin Qin
eb2e892703 [AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

llvm-svn: 194996
2013-11-18 09:20:32 +00:00
Zoran Jovanovic
e87258135d Use instr mapping for microMIPS in llvm-mc.
llvm-svn: 194792
2013-11-15 08:07:34 +00:00
Kevin Qin
0b4fc92580 Add test case for AArch64 NEON instruction set misc.
llvm-svn: 194673
2013-11-14 06:45:17 +00:00
Kevin Qin
47a3b639e3 Implement aarch64 neon instruction class SIMD misc.
llvm-svn: 194656
2013-11-14 02:44:13 +00:00
Jiangning Liu
5a9b5605ba Implement AArch64 NEON instruction set AdvSIMD (table).
llvm-svn: 194648
2013-11-14 01:57:32 +00:00
Richard Sandiford
1817f8f7b4 [SystemZ] Add the general form of BCR
At the moment this is just the MC support.

llvm-svn: 194585
2013-11-13 16:57:53 +00:00
Vladimir Medic
97a94dc2fb Fix bug in .gpword directive parsing.
llvm-svn: 194570
2013-11-13 13:18:04 +00:00
Zoran Jovanovic
feadcc01d7 Support for microMIPS trap instruction with immediate operands.
llvm-svn: 194569
2013-11-13 13:15:03 +00:00
Vladimir Medic
841be82cec This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
llvm-svn: 194562
2013-11-13 09:48:53 +00:00
Tim Northover
872e6a81fc ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

llvm-svn: 194512
2013-11-12 21:32:41 +00:00
Chad Rosier
ba5d2d1be6 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
2013-11-12 19:13:08 +00:00
Artyom Skrobov
7871752687 [ARM] Add support for MVFR2 which is new in ARMv8
llvm-svn: 194416
2013-11-11 19:56:13 +00:00
Chad Rosier
4848250116 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194394
2013-11-11 18:04:07 +00:00
Jim Grosbach
b8435149f5 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

llvm-svn: 194285
2013-11-08 22:33:06 +00:00
Artyom Skrobov
1890ff3a6d [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
llvm-svn: 194263
2013-11-08 16:25:50 +00:00
Artyom Skrobov
d49073b56a [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194262
2013-11-08 16:17:14 +00:00
Artyom Skrobov
ef73b63766 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194261
2013-11-08 16:16:30 +00:00
Zoran Jovanovic
291725e9c0 Test for microMIPS trap instructions.
llvm-svn: 194258
2013-11-08 14:55:31 +00:00
Matheus Almeida
bf40669589 [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.

llvm-svn: 194255
2013-11-08 10:43:11 +00:00
Artyom Skrobov
6b3d6a326b [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
llvm-svn: 194253
2013-11-08 09:16:31 +00:00
Zoran Jovanovic
935364b314 Support for microMIPS trap instructions 1.
llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Vladimir Medic
fac4b6d8bf Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
llvm-svn: 194145
2013-11-06 11:27:05 +00:00
Jiangning Liu
9c0eb8e7ba Implement AArch64 Neon instruction set Perm.
llvm-svn: 194123
2013-11-06 03:35:27 +00:00
Jiangning Liu
1cdd311f06 Implement AArch64 Neon instruction set Bitwise Extract.
llvm-svn: 194118
2013-11-06 02:25:49 +00:00
Tim Northover
d5ccdcd01b ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094
2013-11-05 21:36:02 +00:00
Jiangning Liu
59b8117b0b Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
llvm-svn: 194085
2013-11-05 17:42:05 +00:00
Hao Liu
386d8dd5a6 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
2013-11-05 03:39:32 +00:00
Zoran Jovanovic
134add2b71 Support for microMIPS branch instructions.
llvm-svn: 193992
2013-11-04 14:53:22 +00:00
Chad Rosier
fd7dc7524c [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
llvm-svn: 193816
2013-10-31 22:36:59 +00:00
Chad Rosier
b603d15176 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
llvm-svn: 193798
2013-10-31 20:11:32 +00:00
Chad Rosier
aea5ba449f [AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193790
2013-10-31 19:28:44 +00:00
Amara Emerson
ce9bb052e5 [AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
2013-10-31 09:32:11 +00:00
Tom Roeder
9290de3a99 This commit adds some (but not all) of the x86-64 relocations that are not
currently supported in the ELF object writer, along with a simple test case.

llvm-svn: 193709
2013-10-30 18:47:25 +00:00
Artyom Skrobov
de6ac0d99e [ARM] NEON instructions were erroneously decoded from certain invalid encodings
llvm-svn: 193705
2013-10-30 18:10:09 +00:00
Chad Rosier
02e430c891 [AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193691
2013-10-30 15:19:37 +00:00
Zoran Jovanovic
929213f2ec Support for microMIPS jump instructions
llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Bernard Ogden
121891c3a9 Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.

llvm-svn: 193611
2013-10-29 14:16:09 +00:00
Bernard Ogden
2ff9cbbf41 ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

llvm-svn: 193599
2013-10-29 09:47:35 +00:00
Joerg Sonnenberger
dc4144cbb4 Move the STT_FILE symbols out of the normal symbol table processing for
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".

llvm-svn: 193569
2013-10-29 01:06:17 +00:00
Rafael Espindola
328e8ccb08 Convert another llc -filetype=obj test.
llvm-svn: 193548
2013-10-28 22:17:19 +00:00
Rafael Espindola
1530a2a292 Convert another llc -filetype=obj test.
llvm-svn: 193547
2013-10-28 22:11:47 +00:00
Rafael Espindola
9dbb5cd655 Convert another llc -filetype=obj test.
llvm-svn: 193546
2013-10-28 22:05:05 +00:00
Rafael Espindola
562b3c890e Convert another llc -filetype=obj test.
llvm-svn: 193539
2013-10-28 21:12:15 +00:00
Rafael Espindola
5f82bc3329 Convert another llc -filetype=obj test.
llvm-svn: 193538
2013-10-28 21:06:12 +00:00
Rafael Espindola
4272a090a0 Convert another llc -filetype=obj test.
llvm-svn: 193537
2013-10-28 20:59:41 +00:00
Rafael Espindola
00f2d95c0c Convert another llc -filetype=obj test.
llvm-svn: 193536
2013-10-28 20:54:33 +00:00
Lang Hames
ae80875f08 Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.

When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.

Fixes <rdar://problem/15155975>.

llvm-svn: 193535
2013-10-28 20:51:11 +00:00
Rafael Espindola
c4c4f23851 Convert a llc -filetype=obj test into a llvm-mc test.
llvm-svn: 193534
2013-10-28 20:40:20 +00:00
Logan Chien
043426ee56 [arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.

llvm-svn: 193524
2013-10-28 17:51:12 +00:00
Tim Northover
130230544c ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.

Patch by Gabor Ballabas

llvm-svn: 193403
2013-10-25 12:49:50 +00:00
Tim Northover
fa3626f449 ARM: tweak test to pass on all platforms
A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.

llvm-svn: 193394
2013-10-25 07:34:56 +00:00
Tim Northover
27cc10f26d ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

llvm-svn: 193354
2013-10-24 15:49:39 +00:00
Tim Northover
7ebbaf0161 ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.

llvm-svn: 193342
2013-10-24 12:48:05 +00:00
Tim Northover
0b20ff06da ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

llvm-svn: 193340
2013-10-24 12:22:58 +00:00
Zoran Jovanovic
f202867d24 Added tests for microMIPS relocations 1.
llvm-svn: 193332
2013-10-24 10:55:00 +00:00
Tim Northover
420889afe2 ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.

With some vigorous hand-waving in the error message both problems can be
fixed.

llvm-svn: 193322
2013-10-24 09:37:18 +00:00
Matheus Almeida
5cc3614e90 [mips][msa] Direct Object Emission support for the LSA instruction.
llvm-svn: 193240
2013-10-23 13:20:07 +00:00
Artyom Skrobov
2ef42e5c31 Make ARM hint ranges consistent, and add tests for these ranges
llvm-svn: 193238
2013-10-23 10:14:40 +00:00
David Blaikie
329a9a8a33 MC: Support multiple sections with the same name in the same comdat group
Code review by Eric Christopher and Rafael Espindola.

llvm-svn: 193209
2013-10-22 23:41:52 +00:00
Tim Northover
e4acb9a5a2 ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
2013-10-22 19:00:39 +00:00
Matheus Almeida
06be00bac8 [mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
2013-10-22 09:43:32 +00:00
Matheus Almeida
8cdecf1482 [mips][msa] Direct Object Emission support for LD/ST instructions.
llvm-svn: 193082
2013-10-21 13:07:13 +00:00
Matheus Almeida
49a9f349f1 [mips][msa] Direct Object Emission support for LDI instructions.
llvm-svn: 193081
2013-10-21 12:56:20 +00:00
Matheus Almeida
c0cc50e68b [mips][msa] Direct Object Emission support for MOVE.v.
llvm-svn: 193080
2013-10-21 12:43:54 +00:00
Matheus Almeida
e54e855dbb [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.

llvm-svn: 193078
2013-10-21 12:26:50 +00:00
Matheus Almeida
1fede43958 [mips][msa] Direct Object Emission of SPLAT instruction.
llvm-svn: 193077
2013-10-21 12:07:26 +00:00
Matheus Almeida
1760b2c642 [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
2013-10-21 11:47:56 +00:00
Peter Collingbourne
b815e25b6f Emit DWARF line entries for all data in the instruction stream.
r182712 attempted to do this, but it failed to handle data emitted via
EmitBytes.

llvm-svn: 193041
2013-10-20 02:16:18 +00:00
Hans Wennborg
c1a311233c MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm
This is another (final?) stab at making us able to parse our own asm output
on Windows.

Symbols on Windows often contain @'s and ?'s in their names. Our asm parser
didn't like this. ?'s were not allowed, and @'s were intepreted as trying to
reference PLT/GOT/etc.

We can't just add quotes around the bad names, since e.g. for MinGW, we use gas
to assemble, and it doesn't like quotes in some places (notably in .def
directives).

This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS
assembly.

Differential Revision: http://llvm-reviews.chandlerc.com/D1978

llvm-svn: 193000
2013-10-18 20:46:28 +00:00
Richard Barton
cb6c32ac32 Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov

llvm-svn: 192972
2013-10-18 14:09:49 +00:00
Chad Rosier
163fdd3e73 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192970
2013-10-18 14:03:24 +00:00
Silviu Baranga
0e6bbf1a98 Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
llvm-svn: 192963
2013-10-18 10:18:40 +00:00
Hans Wennborg
33576424a9 Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"
This caused the clang-native-mingw32-win7 buildbot to break.

The assembler was complaining about the following lines that were showing up
in the asm for CrashRecoveryContext.cpp:

  movl  $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax)
  calll "_AddVectoredExceptionHandler@8"
  .def   "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4";
  "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4":
  calll "_RemoveVectoredExceptionHandler@4"

Reverting for now.

llvm-svn: 192940
2013-10-18 02:14:40 +00:00
Chad Rosier
9a6d485c7f [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
2013-10-17 18:12:29 +00:00
Hans Wennborg
822f0080df Re-commit r192758 - MC: quote tricky symbol names in asm output
The reason this got reverted was that the @feat.00 symbol which was emitted
for every TU became quoted, and on cygwin/mingw we use the gas assembler which
couldn't handle the quotes.

This commit fixes the problem by only emitting @feat.00 for win32, where we use
clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no
loss there.

With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since
it uses the Itanium ABI, which doesn't put these funny characters in symbols.

> Because of win32 mangling, we produce symbol and section names with
> funny characters in them, most notably @ characters.
>
> MC would choke on trying to parse its own assembly output. This patch addresses
> that by:
>
> - Making @ trigger quoting of symbol names
> - Also quote section names in the same way
> - Just parse section names like other identifiers (to allow for quotes)
> - Don't assume @ signifies a symbol variant if it is in a string.

llvm-svn: 192859
2013-10-17 01:13:02 +00:00