Chris Lattner
5d1acb831a
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
...
No functionality change.
llvm-svn: 27577
2006-04-11 01:21:43 +00:00
Chris Lattner
3c6e4a1dc9
properly mark vector selects as expanded to select_cc
...
llvm-svn: 27544
2006-04-08 22:59:15 +00:00
Chris Lattner
2ffa288a23
Add VRRC select support
...
llvm-svn: 27543
2006-04-08 22:45:08 +00:00
Nate Begeman
6cdc599d05
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
Chris Lattner
8234bfe18e
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
...
constant pool load.
llvm-svn: 27538
2006-04-08 07:14:26 +00:00
Chris Lattner
e8defcff7d
Change the interface to the predicate that determines if vsplti* can be used.
...
No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
Jim Laskey
fabb0ba736
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
Jim Laskey
b93bc75add
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
Chris Lattner
db7dfe8c61
Add an item
...
llvm-svn: 27470
2006-04-06 23:16:19 +00:00
Chris Lattner
a390188fd4
Make sure to return the result in the right type.
...
llvm-svn: 27469
2006-04-06 23:12:19 +00:00
Chris Lattner
c0680ae07e
Match vpku[hw]um(x,x).
...
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
Chris Lattner
a52d88ee89
Add support for matching vmrg(x,x) patterns
...
llvm-svn: 27463
2006-04-06 22:02:42 +00:00
Chris Lattner
300076cbd8
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
...
llvm-svn: 27457
2006-04-06 21:11:54 +00:00
Chris Lattner
6cf87c1b01
remove two done items
...
llvm-svn: 27453
2006-04-06 19:19:38 +00:00
Chris Lattner
2875bb116e
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
...
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
Chris Lattner
10fa7be550
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
...
vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
Chris Lattner
7f13e50435
Add all of the data stream intrinsics and instructions. woo
...
llvm-svn: 27442
2006-04-05 22:27:14 +00:00
Chris Lattner
338945e669
Fix a typo
...
llvm-svn: 27440
2006-04-05 20:15:25 +00:00
Chris Lattner
d1b47b18ed
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
...
llvm-svn: 27439
2006-04-05 17:39:25 +00:00
Evan Cheng
9e56e97205
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
...
llvm-svn: 27433
2006-04-05 06:09:26 +00:00
Chris Lattner
ee971bedf2
add vsl
...
llvm-svn: 27425
2006-04-05 01:16:22 +00:00
Chris Lattner
993209029f
add vmladduhm
...
llvm-svn: 27423
2006-04-05 00:49:48 +00:00
Chris Lattner
66c3b75644
Add m[tf]vscr instructions.
...
llvm-svn: 27421
2006-04-05 00:03:57 +00:00
Chris Lattner
10394b1c42
add a note
...
llvm-svn: 27419
2006-04-04 23:45:11 +00:00
Chris Lattner
e7a52b473f
Add missing byte merges.
...
llvm-svn: 27418
2006-04-04 23:43:56 +00:00
Chris Lattner
ab137b431f
Add FP -> Int Conversions
...
llvm-svn: 27417
2006-04-04 23:25:02 +00:00
Chris Lattner
6cf881590f
add average intrinsics
...
llvm-svn: 27416
2006-04-04 23:14:00 +00:00
Chris Lattner
59c4add58a
add a note
...
llvm-svn: 27414
2006-04-04 22:43:55 +00:00
Chris Lattner
d1483ca1ad
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
...
llvm-svn: 27413
2006-04-04 22:28:35 +00:00
Chris Lattner
4e99e6dfdd
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
...
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
Chris Lattner
2bf9c8cc18
Plug in the byte and short splats
...
llvm-svn: 27387
2006-04-04 00:05:13 +00:00
Chris Lattner
0128e4d335
Revert accidentally committed hunks.
...
llvm-svn: 27386
2006-04-03 23:58:04 +00:00
Chris Lattner
57b9e01b3e
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
...
llvm-svn: 27385
2006-04-03 23:55:43 +00:00
Chris Lattner
eb9684f6a4
Force use of a frame-pointer if there is anything on the stack that is aligned
...
more than the OS keeps the stack aligned.
llvm-svn: 27381
2006-04-03 22:03:29 +00:00
Chris Lattner
c65511b05c
Add the full set of min/max instructions
...
llvm-svn: 27372
2006-04-03 15:58:28 +00:00
Chris Lattner
fa82c33ae7
add a note
...
llvm-svn: 27360
2006-04-02 07:20:00 +00:00
Chris Lattner
8ba4723c74
Inform the dag combiner that the predicate compares only return a low bit.
...
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
Chris Lattner
8967316b8c
Remove done item
...
llvm-svn: 27351
2006-04-02 05:28:54 +00:00
Chris Lattner
9c24ec6de5
add a note
...
llvm-svn: 27348
2006-04-02 03:59:11 +00:00
Chris Lattner
da4217646a
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
...
"vspltisb v0, 8" instead of a constant pool load.
llvm-svn: 27335
2006-04-02 00:43:36 +00:00
Chris Lattner
38318b2706
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
...
llvm-svn: 27331
2006-04-01 22:41:47 +00:00
Chris Lattner
32bb17a5f3
Shrinkify some more intrinsic definitions.
...
llvm-svn: 27322
2006-03-31 22:41:56 +00:00
Chris Lattner
12e9ce7104
Pull operand asm string into base class, shrinkifying intrinsic definitions.
...
No functionality change.
llvm-svn: 27320
2006-03-31 22:34:05 +00:00
Chris Lattner
3d6e5f8a05
Fix 80 column violations :)
...
llvm-svn: 27315
2006-03-31 21:57:36 +00:00
Chris Lattner
d66dd2a4ee
fix a pasto
...
llvm-svn: 27308
2006-03-31 21:19:06 +00:00
Chris Lattner
28219f34bc
Add vperm support for all datatypes
...
llvm-svn: 27307
2006-03-31 20:00:35 +00:00
Chris Lattner
336d6646ab
Rearrange code a bit
...
llvm-svn: 27306
2006-03-31 19:52:36 +00:00
Chris Lattner
786f782398
Add, sub and shuffle are legal for all vector types
...
llvm-svn: 27305
2006-03-31 19:48:58 +00:00
Chris Lattner
d27ced882b
add a note
...
llvm-svn: 27302
2006-03-31 19:00:22 +00:00
Chris Lattner
e3774da014
note to self: *save* file, then check it in
...
llvm-svn: 27291
2006-03-31 06:04:53 +00:00
Chris Lattner
95d358dbdb
Implement an item from the readme, folding vcmp/vcmp. instructions with
...
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
llvm-svn: 27290
2006-03-31 06:02:07 +00:00
Chris Lattner
560f734320
compactify some more instruction definitions
...
llvm-svn: 27288
2006-03-31 05:38:32 +00:00
Chris Lattner
2c3d6bdb55
Compactify comparisons.
...
llvm-svn: 27287
2006-03-31 05:32:57 +00:00
Chris Lattner
e330741a6c
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
llvm-svn: 27285
2006-03-31 05:13:27 +00:00
Chris Lattner
a7a7c035b3
These are done
...
llvm-svn: 27284
2006-03-31 04:53:21 +00:00
Chris Lattner
a31d719e0a
Mark INSERT_VECTOR_ELT as expand
...
llvm-svn: 27276
2006-03-31 01:48:55 +00:00
Chris Lattner
87d3a2e045
Add the rest of the vmul instructions and the vmulsum* instructions.
...
llvm-svn: 27268
2006-03-30 23:39:06 +00:00
Chris Lattner
22b7e551f1
Use a new tblgen feature to significantly shrinkify instruction definitions that
...
directly correspond to intrinsics.
llvm-svn: 27266
2006-03-30 23:21:27 +00:00
Chris Lattner
6aca6013d2
Add a bunch of new instructions for intrinsics.
...
llvm-svn: 27265
2006-03-30 23:07:36 +00:00
Chris Lattner
1a773f8f18
add a note
...
llvm-svn: 27243
2006-03-29 00:24:13 +00:00
Chris Lattner
93559450b8
add a note
...
llvm-svn: 27227
2006-03-28 18:56:23 +00:00
Jim Laskey
eb38a3e83a
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Nate Begeman
d432d66cc8
Fix a couple typos
...
llvm-svn: 27216
2006-03-28 04:18:18 +00:00
Nate Begeman
5a82c8ccbd
Add a few more altivec intrinsics
...
llvm-svn: 27215
2006-03-28 04:15:58 +00:00
Chris Lattner
a570305421
implement a bunch more intrinsics.
...
llvm-svn: 27209
2006-03-28 02:29:37 +00:00
Chris Lattner
ac98e20cc9
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
llvm-svn: 27205
2006-03-28 01:43:22 +00:00
Chris Lattner
d5da541d42
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
Jim Laskey
8688957c53
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
Chris Lattner
dab8425129
Add a bunch of notes from my journey thus far.
...
llvm-svn: 27170
2006-03-27 07:41:00 +00:00
Chris Lattner
f1d6a9483f
Split out altivec notes into their own README
...
llvm-svn: 27168
2006-03-27 07:04:16 +00:00
Chris Lattner
4b0fc38fe7
Fix the JIT encoding of VSEL
...
llvm-svn: 27160
2006-03-27 03:34:17 +00:00
Chris Lattner
b5efa3e0f5
Fix the JIT encoding of VSPLTI*
...
llvm-svn: 27159
2006-03-27 03:28:57 +00:00
Nate Begeman
3d518334b9
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
Chris Lattner
03ad35fd49
add vsel
...
llvm-svn: 27153
2006-03-26 22:38:43 +00:00
Chris Lattner
65a455b060
Codegen vector predicate compares.
...
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
Evan Cheng
b17bbf8ccb
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
...
llvm-svn: 27149
2006-03-26 09:52:32 +00:00
Chris Lattner
f0c36b99e6
Add all of the altivec comparison instructions. Add patterns for the
...
non-predicate altivec compare intrinsics.
llvm-svn: 27143
2006-03-26 04:57:17 +00:00
Chris Lattner
4e0a78ea30
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
...
intrinsics.
llvm-svn: 27142
2006-03-26 02:39:02 +00:00
Chris Lattner
d33ef7a1bc
implement the vsldoi intrinsic.
...
llvm-svn: 27139
2006-03-26 00:41:48 +00:00
Chris Lattner
7d557e00f3
fix the pattern for vandc, it's NOT vnand
...
llvm-svn: 27136
2006-03-25 23:10:40 +00:00
Chris Lattner
88a0c65463
add patterns for VANDC/VNOR, implementing
...
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
llvm-svn: 27135
2006-03-25 23:05:29 +00:00
Chris Lattner
f80b39f9b1
Add some logical operations
...
llvm-svn: 27127
2006-03-25 22:16:05 +00:00
Chris Lattner
d2823658b4
implement a bunch of intrinsics
...
llvm-svn: 27118
2006-03-25 08:01:02 +00:00
Chris Lattner
cb5f9269a9
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
...
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
llvm-svn: 27117
2006-03-25 07:51:43 +00:00
Chris Lattner
57064915a6
Add some basic patterns for other datatypes
...
llvm-svn: 27116
2006-03-25 07:39:07 +00:00
Chris Lattner
7f5fba9c67
add all supported formats to the vector register file
...
llvm-svn: 27115
2006-03-25 07:36:56 +00:00
Chris Lattner
2fa3a6c436
Add support for __builtin_altivec_vnmsubfp /vmaddfp
...
llvm-svn: 27112
2006-03-25 07:05:55 +00:00
Chris Lattner
e199d55073
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
Chris Lattner
0899b16b2d
Codegen things like:
...
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
llvm-svn: 27106
2006-03-25 06:12:06 +00:00
Jim Laskey
1716e53341
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
Chris Lattner
8840036091
add another note
...
llvm-svn: 27077
2006-03-24 20:04:27 +00:00
Chris Lattner
21abff3712
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
...
llvm-svn: 27069
2006-03-24 18:24:43 +00:00
Chris Lattner
3133dafd4b
Like the comment says, prefer to use the implicit add done by [r+r] addressing
...
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
llvm-svn: 27068
2006-03-24 17:58:06 +00:00
Chris Lattner
303dc30593
Disable the i32->float G5 optimization. It is unsafe, as documented in the
...
comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
llvm-svn: 27060
2006-03-24 07:53:47 +00:00
Chris Lattner
ba4966c16c
add support for using vxor to build zero vectors. This implements
...
Regression/CodeGen/PowerPC/vec_zero.ll
llvm-svn: 27059
2006-03-24 07:48:08 +00:00
Chris Lattner
ace2d0d227
Gabor points out that we can't spell. :)
...
llvm-svn: 27049
2006-03-24 07:12:19 +00:00
Chris Lattner
2e5162fa6e
add a note
...
llvm-svn: 27000
2006-03-23 21:28:44 +00:00
Chris Lattner
974982c89c
Add PPC vector bit-convert support
...
llvm-svn: 26995
2006-03-23 19:54:27 +00:00
Jim Laskey
cec9c18c62
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
Jim Laskey
f3cc740d75
Change interface to DwarfWriter.
...
llvm-svn: 26991
2006-03-23 18:09:44 +00:00
Chris Lattner
89e0790edb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
Chris Lattner
5141ebb2c4
This has been implemented. Tweak it into another note
...
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
Chris Lattner
f84f3bf95b
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
Chris Lattner
cfbce5186a
Add support for "ri" addressing modes where the immediate is a 14-bit field
...
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
Chris Lattner
2e606dc60f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
Chris Lattner
31a93c7740
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
Chris Lattner
140be98ab8
Don't emit pseudo instructions!
...
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
Nate Begeman
4bd73df4bd
Update readme
...
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
Chris Lattner
414fed4108
Print absolute memory references like this:
...
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
Chris Lattner
6417236c41
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
...
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
Chris Lattner
acb2506622
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
Chris Lattner
9e611a25c7
minor note
...
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
Chris Lattner
cdc4657988
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
Chris Lattner
a498dd25d9
remove dead variable
...
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
Chris Lattner
978628896b
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
Chris Lattner
5c994b8c63
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
Chris Lattner
fb0e160aa5
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
Evan Cheng
57da1afbc8
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
Chris Lattner
dc3605efdb
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
Chris Lattner
8faa2cf693
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
Chris Lattner
4b7aa59bbc
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
Chris Lattner
1cdeda1c5a
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
Chris Lattner
c230af9810
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
Chris Lattner
bea056ecf2
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
Chris Lattner
0e56cf0d94
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
Chris Lattner
65e6e12dca
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
Chris Lattner
6f502da274
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
Chris Lattner
ada41aad4d
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
Chris Lattner
789570bafb
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
Chris Lattner
80f9f7138a
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
Chris Lattner
89bc332152
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
Chris Lattner
a9b4a2ab99
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
Chris Lattner
d3910ca755
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
Chris Lattner
b46a4c28ad
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
Chris Lattner
1bd0aaf2b8
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
Nate Begeman
793c8136ae
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
Nate Begeman
42736d46b2
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
Chris Lattner
87dbd49cbe
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
Nate Begeman
63c4456867
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
Chris Lattner
f2008cb73b
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
Chris Lattner
8a756c5171
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
Chris Lattner
57773fdac1
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
Chris Lattner
661ee5d3c1
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
Evan Cheng
cad75d9f0c
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
Chris Lattner
7f5361757b
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
Nate Begeman
cbca1b3d14
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
Chris Lattner
b5d0896994
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
Nate Begeman
e371cb595a
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
Chris Lattner
392087f5bd
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
Evan Cheng
ae7469b2c5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
Evan Cheng
7ec94f2ff7
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
Chris Lattner
d0505331d2
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
Chris Lattner
3aff8e6acf
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
Chris Lattner
9898674f99
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
Chris Lattner
ba10d4e4ab
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
Chris Lattner
19b93158c1
blr is a branch too
...
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
Chris Lattner
2370965e55
teach the JIT to encode vector registers
...
llvm-svn: 26697
2006-03-10 20:19:50 +00:00
Chris Lattner
3f23d22d3f
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
Chris Lattner
24aa564456
add a note
...
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
Jim Laskey
91d5ce2531
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
Chris Lattner
27f87a6955
add another missing store.
...
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
Chris Lattner
dfdeec73bc
add a couple more load/store instrs, add a newline to the end of file.
...
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
Nate Begeman
a8bc3c0c3c
This kinda sorta implements "things that have to lead a dispatch group".
...
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
Chris Lattner
842436586c
add some new instructions to the classifier. With this, we correctly insert
...
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
Chris Lattner
0cd4bd574c
add some comments that describe what we model
...
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
Chris Lattner
4cd6cd499d
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
...
flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
Chris Lattner
ae34bbf56b
add a note
...
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
Chris Lattner
af44ead7f3
implement TII::insertNoop
...
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
Chris Lattner
6b0947c277
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
Chris Lattner
317021b6c4
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
Chris Lattner
caec0d887c
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
Chris Lattner
137c02aa60
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
Chris Lattner
6ba976b557
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
Evan Cheng
ebe1f272b7
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
Chris Lattner
9f70a7924d
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
Chris Lattner
866634d77f
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
Nate Begeman
56a4dafd8d
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
Chris Lattner
bc35137363
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
Chris Lattner
3d451516ec
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
Evan Cheng
2720cd1d7e
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
Chris Lattner
cdbd9d6d4c
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
Evan Cheng
305141c1ba
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
Jim Laskey
b62a583c99
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
Chris Lattner
6bb2c3e9cd
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner
a124432746
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
Evan Cheng
c4cda2b89a
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
Nate Begeman
9c0ab71f4a
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Evan Cheng
131901cbb8
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
Chris Lattner
af26f481e9
If we have zero initialized data with external linkage, use .zerofill to
...
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
llvm-svn: 26185
2006-02-14 22:18:23 +00:00
Chris Lattner
02f3db9781
Make sure that weak functions are aligned properly
...
llvm-svn: 26181
2006-02-14 20:42:33 +00:00
Chris Lattner
9db5a1fd19
Switch to using getCALLSEQ_START instead of using our own creation calls
...
llvm-svn: 26142
2006-02-13 08:55:29 +00:00
Nate Begeman
7261b82dd7
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
llvm-svn: 26136
2006-02-12 09:09:52 +00:00
Evan Cheng
6bd0f9c4ba
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
Evan Cheng
521e5a1bfe
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
Chris Lattner
2e1a495967
Darwin doesn't support #APP/#NO_APP
...
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
Chris Lattner
47ef931412
Rename BSel -> PPCBSel for the benefit of doxygen users.
...
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
2006-02-08 19:33:26 +00:00
Chris Lattner
86d1dcf613
Emit the 'mr' pseudoop for easier reading.
...
llvm-svn: 26053
2006-02-08 06:56:40 +00:00
Chris Lattner
881c8c12ff
Move emails from nate into public places
...
llvm-svn: 26051
2006-02-08 06:43:51 +00:00
Chris Lattner
abaa15898f
Implement getConstraintType for PPC.
...
llvm-svn: 26042
2006-02-07 20:16:30 +00:00
Chris Lattner
50af3c6eb7
Add the simple PPC integer constraints
...
llvm-svn: 26027
2006-02-07 00:47:13 +00:00
Chris Lattner
b6fae6bad7
Change prototype
...
llvm-svn: 26022
2006-02-06 22:18:19 +00:00
Jim Laskey
62908083eb
We seem to have settled to __DWARF for section name.
...
llvm-svn: 26015
2006-02-06 14:16:15 +00:00
Evan Cheng
9fb67ea859
Complex pattern isel code shouldn't select nodes.
...
llvm-svn: 26010
2006-02-05 08:45:01 +00:00
Evan Cheng
fb902782e8
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
Chris Lattner
59378e7675
add a note
...
llvm-svn: 25984
2006-02-05 05:27:35 +00:00
Chris Lattner
085a324bfc
Use the asmprinter to find out what the preferred alignment of a global is.
...
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
llvm-svn: 25979
2006-02-05 01:30:45 +00:00
Nate Begeman
ba19f3f93c
Remove some stuff that now works
...
llvm-svn: 25963
2006-02-04 07:29:35 +00:00
Chris Lattner
393e9d10dd
add a note
...
llvm-svn: 25944
2006-02-03 22:06:45 +00:00
Chris Lattner
172cf85d48
remove some target-indep and implemented notes
...
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
Nate Begeman
85f3c9f566
Flesh out a couple of the items in the README
...
llvm-svn: 25928
2006-02-03 05:17:06 +00:00
Chris Lattner
06f54e7cb3
Add a note
...
llvm-svn: 25921
2006-02-03 01:49:49 +00:00
Chris Lattner
66d0341e73
update a note
...
llvm-svn: 25918
2006-02-02 23:50:22 +00:00
Nate Begeman
09bdfffaa6
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
...
llvm-svn: 25916
2006-02-02 21:07:50 +00:00
Chris Lattner
8337a1050d
implement isStoreToStackSlot for PPC
...
llvm-svn: 25914
2006-02-02 20:16:12 +00:00
Chris Lattner
15cb732cd7
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
Chris Lattner
c434ee61a3
new example
...
llvm-svn: 25903
2006-02-02 07:37:11 +00:00
Nate Begeman
dd4acf9710
Update the README
...
llvm-svn: 25902
2006-02-02 07:27:56 +00:00
Chris Lattner
d202c4d3cc
add a method
...
llvm-svn: 25884
2006-02-01 22:38:46 +00:00
Chris Lattner
821f93a659
add a note
...
llvm-svn: 25876
2006-02-01 17:54:23 +00:00
Nate Begeman
0be60963bd
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
Chris Lattner
c270dd87a9
another testcase.
...
llvm-svn: 25862
2006-02-01 00:28:12 +00:00
Evan Cheng
f115c17f23
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
Chris Lattner
892fe31362
add info about the inline asm register constraints for PPC
...
llvm-svn: 25853
2006-01-31 19:20:21 +00:00
Nate Begeman
7a83bb4285
Codegen
...
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
llvm-svn: 25848
2006-01-31 08:17:29 +00:00
Chris Lattner
186b5f0887
example nate pointed out
...
llvm-svn: 25841
2006-01-31 07:16:34 +00:00
Chris Lattner
830b1ad8cf
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
Chris Lattner
2ab7f21d20
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
Chris Lattner
4c6384a412
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
Chris Lattner
00e9ba5526
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
Chris Lattner
6c4173145e
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
Chris Lattner
5f0a3df176
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
Chris Lattner
d2eb15f467
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
Chris Lattner
170727421b
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
Nate Begeman
a46156da35
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
Chris Lattner
6a5d2450a3
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
Chris Lattner
59a4f3f637
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
Nate Begeman
d2c6fbef4a
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Evan Cheng
77885c204d
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
Chris Lattner
20d4194a0d
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Jim Laskey
583aae3110
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
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Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
Evan Cheng
7da6daadc7
Set SchedulingForLatency to be the default scheduling preference for all.
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llvm-svn: 25607
2006-01-25 18:52:42 +00:00
Nate Begeman
c29fac7fce
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
c368fb710f
Default scheduling preference is SchedulingForLatency.
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llvm-svn: 25603
2006-01-25 09:15:54 +00:00
Jim Laskey
18ba7ce7b3
Crude Dwarf global variable debugging.
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llvm-svn: 25569
2006-01-24 00:49:18 +00:00
Chris Lattner
aafc339b4e
Add explicit #includes of <iostream>
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llvm-svn: 25515
2006-01-22 23:41:00 +00:00
Chris Lattner
adff158fbd
Add explicit #includes of <iostream>
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llvm-svn: 25509
2006-01-22 22:53:01 +00:00
Chris Lattner
1ecabc5a6f
trivial formatting improvement: don't insert extra blank lines between .comm
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vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
Chris Lattner
60bc56e930
add a note
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llvm-svn: 25439
2006-01-19 02:09:38 +00:00