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Commit Graph

209863 Commits

Author SHA1 Message Date
Jessica Paquette
c4d2d8a4de [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load
This is a restricted version of the combine in `DAGCombiner::MatchLoadCombine`.
(See D27861)

This tries to recognize patterns like below (assuming a little-endian target):

```
s8* x = ...
s32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24)
->
s32 val = *((i32)a)

s8* x = ...
s32 val = a[3] | (a[2] << 8) | (a[1] << 16) | (a[0] << 24)
->
s32 val = BSWAP(*((s32)a))
```

(This patch also handles the big-endian target case as well, in which the first
example above has a BSWAP, and the second example above does not.)

To recognize the pattern, this searches from the last G_OR in the expression
tree.

E.g.

```
    Reg   Reg
     \    /
      OR_1   Reg
       \    /
        OR_2
          \     Reg
           .. /
          Root
```

Each non-OR register in the tree is put in a list. Each register in the list is
then checked to see if it's an appropriate load + shift logic.

If every register is a load + potentially a shift, the combine checks if those
loads + shifts, when OR'd together, are equivalent to a wide load (possibly with
a BSWAP.)

To simplify things, this patch

(1) Only handles G_ZEXTLOADs (which appear to be the common case)
(2) Only works in a single MachineBasicBlock
(3) Only handles G_SHL as the bit twiddling to stick the small load into a
    specific location

An IR example of this is here: https://godbolt.org/z/4sP9Pj (lifted from
test/CodeGen/AArch64/load-combine.ll)

At -Os on AArch64, this is a 0.5% code size improvement for CTMark/sqlite3,
and a 0.4% improvement for CTMark/7zip-benchmark.

Also fix a bug in `isPredecessor` which caused it to fail whenever `DefMI` was
the first instruction in the block.

Differential Revision: https://reviews.llvm.org/D94350
2021-01-19 10:24:27 -08:00
Fraser Cormack
00b92c78b2 [RISCV] Add ISel patterns for scalable mask exts & truncs
Original patch by @rogfer01.

This patch adds support for sign-, zero-, and any-extension from
scalable mask vector types to integer vector types, as well as
truncation in the opposite direction.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94590
2021-01-19 18:13:15 +00:00
Abhina Sreeskantharajan
74052a31cc [SystemZ][z/OS] Fix Permission denied pattern matching
On z/OS, the error message "EDC5111I Permission denied." is not matched correctly in lit tests. This patch updates the check expression to match successfully.

Differential Revision: https://reviews.llvm.org/D94432
2021-01-19 13:05:52 -05:00
David Green
04f2bf7a46 [ARM] Expand vXi1 VSELECT's
We have no lowering for VSELECT vXi1, vXi1, vXi1, so mark them as
expanded to turn them into a series of logical operations.

Differential Revision: https://reviews.llvm.org/D94946
2021-01-19 17:56:50 +00:00
Nikita Popov
d56d32f92d [ValueTracking] Strengthen impliesPoison reasoning
Split impliesPoison into two recursive walks, one over V, the
other over ValAssumedPoison. This allows us to reason about poison
implications in a number of additional cases that are important
in practice. This is a generalized form of D94859, which handles
the cmp to cmp implication in particular.

Differential Revision: https://reviews.llvm.org/D94866
2021-01-19 18:04:23 +01:00
Jay Foad
a8ed61d9be [AMDGPU] Fix test case for D94010 2021-01-19 16:46:47 +00:00
Jay Foad
911caa6874 [AMDGPU] Simplify test case for D94010 2021-01-19 16:36:43 +00:00
Fraser Cormack
8876d555ae [RISCV] Extend RVV VType info with the type's AVL (NFC)
This patch factors out the "VLMax" operand passed to most
scalable-vector ISel patterns into a property of each VType.

This is seen as a preparatory change to allow RVV in the future to
more easily support fixed-length vector types with constrained vector
lengths, with the AVL operand set to the length of the fixed-length
vector. It has no effect on the scalable code generation path.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D94594
2021-01-19 15:46:56 +00:00
David Green
c7d5648431 [ARM] Add MVE add.sat costs
This adds some basic MVE sadd_sat/ssub_sat/uadd_sat/usub_sat costs,
based on when the instruction is legal. With smaller than legal types
that are promoted we generate shr(qadd(shl, shl)), so the cost is 4
appropriately.

Differential Revision: https://reviews.llvm.org/D94958
2021-01-19 15:38:46 +00:00
Valentin Clement
715d713b9e [flang][directive] Get rid of flangClassValue in TableGen
The TableGen emitter for directives has two slots for flangClass information and this was mainly
to be able to keep up with the legacy openmp parser at the time. Now that all clauses are encapsulated in
AccClause or OmpClause, these two strings are not necessary anymore and were the the source of couple
of problem while working with the generic structure checker for OpenMP.
This patch remove the flangClassValue string from DirectiveBase.td and use the string flangClass as the
placeholder for the encapsulated class.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D94821
2021-01-19 10:28:46 -05:00
Victor Huang
c88264fd68 [PowerPC] Fix the check for the instruction using FRSP/XSRSP output register
When performing peephole optimization to simplify the code, after removing
passed FPSP/XSRSP instruction we will set any uses of that FRSP/XSRSP to the
source of the FRSP/XSRSP.

We are finding the machine instruction using virtual register holding FRSP/XSRSP
results by searching all following instructions and encountering an issue
that the first use of the virtual register is a debug MI causing:
1. virtual register in the debug MI removed unexpectedly.
2. virtual register used in non-debug MI not replaced with the source of
  FRSP/XSRSP. which stays in a undef status.

This patch fix the issue by only searching non-debug machine instruction using
virtual register holding FRSP/XSRSP results when the vr only has one non debug
usage.

Differential Revisien: https://reviews.llvm.org/D94711
Reviewed by: nemanjai
2021-01-19 09:20:03 -06:00
Raul Tambre
732857e164 [CMake] Remove dead code setting policies to NEW
cmake_minimum_required(VERSION) calls cmake_policy(VERSION),
which sets all policies up to VERSION to NEW.
LLVM started requiring CMake 3.13 last year, so we can remove
a bunch of code setting policies prior to 3.13 to NEW as it
no longer has any effect.

Reviewed By: phosek, #libunwind, #libc, #libc_abi, ldionne

Differential Revision: https://reviews.llvm.org/D94374
2021-01-19 17:19:36 +02:00
David Green
218cbd9ab8 [ARM] Expand add.sat/sub.sat cost checks. NFC 2021-01-19 15:06:06 +00:00
Florian Hahn
46a4268cbe [LoopRotate] Calls not lowered to calls should not block rotation.
83daa49758a1 made loop-rotate more conservative in the presence of
function calls in the prepare-for-lto stage. The code did not properly
account for calls that are no actual function calls, like calls to
intrinsics. This patch updates the code to ensure only calls that are
lowered to actual calls are considered inline candidates.
2021-01-19 14:37:36 +00:00
Simon Pilgrim
3e379c7903 [X86] Regenerate fmin/fmax reduction tests
Add missing check-prefixes + v1f32 tests
2021-01-19 14:28:44 +00:00
Tim Northover
ed1f4159c7 AArch64: add apple-a14 as a CPU
This CPU supports all v8.5a features except BTI, and so identifies as v8.5a to
Clang. A bit weird, but the best way for things like xnu to detect the new
features it cares about.
2021-01-19 14:04:53 +00:00
Hans Wennborg
12b7677de1 [ThinLTO] Also prune Thin-* files from the ThinLTO cache
Such files (Thin-%%%%%%.tmp.o) are supposed to be deleted immediately
after they're used (either by renaming or deletion). However, we've seen
instances on Windows where this doesn't happen, probably due to the
filesystem being flaky. This is effectively a resource leak which has
prevented us from using the ThinLTO cache on Windows.

Since those temporary files are in the thinlto cache directory which we
prune periodically anyway, allowing them to be pruned too seems like a
tidy way to solve the problem.

Differential revision: https://reviews.llvm.org/D94962
2021-01-19 14:43:49 +01:00
Med Ismail Bennani
3496691e63 [llvm/Orc] Fix ExecutionEngine module build breakage
This patch updates the llvm module map to reflect changes made in
`24672ddea3c97fd1eca3e905b23c0116d7759ab8` and fixes the module builds
(`-DLLVM_ENABLE_MODULES=On`).

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2021-01-19 14:39:06 +01:00
Caroline Concatto
90b2e7be56 [AArch64][SVE]Add cost model for vector reduce for scalable vector
This patch computes the cost for vector.reduce<operand> for scalable vectors.
The cost is split into two parts:  the legalization cost and the horizontal
reduction.

Differential Revision: https://reviews.llvm.org/D93639
2021-01-19 11:54:16 +00:00
Simon Pilgrim
6007680bfe [X86][SSE] combineVectorSignBitsTruncation - fold trunc(srl(x,c)) -> packss(sra(x,c))
If a srl doesn't introduce any sign bits into the truncated result, then replace with a sra to let us use a PACKSS truncation - fixes a regression noticed in D56387 on pre-SSE41 targets that don't have PACKUSDW.
2021-01-19 11:04:13 +00:00
Hans Wennborg
78cd25d7f9 Revert 5238e7b302 "[InstCombine] Replace one-use select operand based on condition"
This caused a miscompile in Chromium, see comments on the codereview for
discussion and pointer to a reproducer.

> InstCombine already performs a fold where X == Y ? f(X) : Z is
> transformed to X == Y ? f(Y) : Z if f(Y) simplifies. However,
> if f(X) only has one use, then we can always directly replace the
> use inside the instruction. To actually be profitable, limit it to
> the case where Y is a non-expr constant.
>
> This could be further extended to replace uses further up a one-use
> instruction chain, but for now this only looks one level up.
>
> Among other things, this also subsumes D94860.
>
> Differential Revision: https://reviews.llvm.org/D94862

This also reverts the follow-up
a003f26539cf4db744655e76c41f4c4a8913f116:

> [llvm] Prevent infinite loop in InstCombine of select statements
>
> This fixes an issue where the RHS and LHS the comparison operation
> creating the predicate were swapped back and forth forever.
>
> Differential Revision: https://reviews.llvm.org/D94934
2021-01-19 11:50:56 +01:00
Jay Foad
a816310ce3 [AMDGPU] Simplify AMDGPUInstPrinter::printExpSrcN. NFC.
Change-Id: Idd7f47647bc0faa3ad6f61f44728c0f20540ec00
2021-01-19 10:39:56 +00:00
Florian Hahn
d596025713 [LoopRotate] Add PrepareForLTO stage, avoid rotating with inline cands.
D84108 exposed a bad interaction between inlining and loop-rotation
during regular LTO, which is causing notable regressions in at least
CINT2006/473.astar.

The problem boils down to: we now rotate a loop just before the vectorizer
which requires duplicating a function call in the preheader when compiling
the individual files ('prepare for LTO'). But this then prevents further
inlining of the function during LTO.

This patch tries to resolve this issue by making LoopRotate more
conservative with respect to rotating loops that have inline-able calls
during the 'prepare for LTO' stage.

I think this change intuitively improves the current situation in
general. Loop-rotate tries hard to avoid creating headers that are 'too
big'. At the moment, it assumes all inlining already happened and the
cost of duplicating a call is equal to just doing the call. But with LTO,
inlining also happens during full LTO and it is possible that a previously
duplicated call is actually a huge function which gets inlined
during LTO.

From the perspective of LV, not much should change overall. Most loops
calling user-provided functions won't get vectorized to start with
(unless we can infer that the function does not touch memory, has no
other side effects). If we do not inline the 'inline-able' call during
the LTO stage, we merely delayed loop-rotation & vectorization. If we
inline during LTO, chances should be very high that the inlined code is
itself vectorizable or the user call was not vectorizable to start with.

There could of course be scenarios where we inline a sufficiently large
function with code not profitable to vectorize, which would have be
vectorized earlier (by scalarzing the call). But even in that case,
there probably is no big performance impact, because it should be mostly
down to the cost-model to reject vectorization in that case. And then
the version with scalarized calls should also not be beneficial. In a way,
LV should have strictly more information after inlining and make more
accurate decisions (barring cost-model issues).

There is of course plenty of room for things to go wrong unexpectedly,
so we need to keep a close look at actual performance and address any
follow-up issues.

I took a look at the impact on statistics for
MultiSource/SPEC2000/SPEC2006. There are a few benchmarks with fewer
loops rotated, but no change to the number of loops vectorized.

Reviewed By: sanwou01

Differential Revision: https://reviews.llvm.org/D94232
2021-01-19 10:15:29 +00:00
Yvan Roux
178bc607c9 [ARM][MachineOutliner] Add stack fixup feature
This patch handles cases where we have to save/restore the link register
into the stack and and load/store instruction which use the stack are
part of the outlined region. It checks that there will be no overflow
introduced by the new offset and fixup these instructions accordingly.

Differential Revision: https://reviews.llvm.org/D92934
2021-01-19 10:59:09 +01:00
Fraser Cormack
d6f7a6374a [RISCV] Add scalable-vector integer extension patterns
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94694
2021-01-19 09:30:36 +00:00
Tres Popp
f0a947fd0e [llvm] Prevent infinite loop in InstCombine of select statements
This fixes an issue where the RHS and LHS the comparison operation
creating the predicate were swapped back and forth forever.

Differential Revision: https://reviews.llvm.org/D94934
2021-01-19 10:31:48 +01:00
serge-sans-paille
1734c4008a [lit] Harmonize lit and llvm versionning
In addition to consistency, we'll hit a wall when 11.1.0 gets released, because
we cannot represent it with lit versioning scheme.

Differential Revision: https://reviews.llvm.org/D94157
2021-01-19 10:27:14 +01:00
Lang Hames
3c8ce89cc8 [ORC] Move LookupRequest from OrcShared to Orc.
It depends on Orc types (SymbolLookupSet), so can't be part of OrcShared.
2021-01-19 20:23:47 +11:00
Tres Popp
29b8ccfd0c [llvm][nvptx] add atomicity to counter in ISelLowering
Previously uniqueCallSite could have race conditions between different
threads. Now it is accessed with an atomic RMW and will be unique
between different threads.

Differential Revision: https://reviews.llvm.org/D94784
2021-01-19 10:20:20 +01:00
David Sherwood
6c0762e51e [NFC] Make remaining cost functions in LoopVectorize.cpp use InstructionCost
A previous patch has already changed getInstructionCost to return
an InstructionCost type. This patch changes the other various
getXXXCost functions to return an InstructionCost too. This is a
non-functional change - I've added a few asserts that the costs
are valid in places where we're selecting between vector call
and intrinsic costs. However, since we don't yet return invalid
costs from any of the TTI implementations these asserts should
not fire.

See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Differential Revision: https://reviews.llvm.org/D94065
2021-01-19 09:08:40 +00:00
Andy Wingo
b4f7ebdf5e [WebAssembly] Change prefix on data segment flags to WASM_DATA_SEGMENT
Element sections will also need flags, so we shouldn't squat the
WASM_SEGMENT namespace.

Depends on D90948.

Differential Revision: https://reviews.llvm.org/D92315
2021-01-19 09:40:42 +01:00
Andy Wingo
6ddb7e7525 [WebAssembly] call_indirect issues table number relocs
This patch changes to make call_indirect explicitly refer to the
corresponding function table, residualizing TABLE_NUMBER relocs against
it.

With this change, wasm-ld now sees all references to tables, and can
link multiple tables.

Differential Revision: https://reviews.llvm.org/D90948
2021-01-19 09:32:45 +01:00
ShihPo Hung
2b1fcde239 [RISCV] Add intrinsics for vector AMO operations
Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
    vamomin, vamomax, vamominu, vamomaxu intrinsics.

Reviewed By: craig.topper, khchen

Differential Revision: https://reviews.llvm.org/D94589
2021-01-18 23:11:10 -08:00
Yang Fan
e3d3775702 [NFC][AIX][XCOFF] Fix compile warning on strncpy
GCC warning:
```
In file included from /usr/include/string.h:495,
                 from /usr/include/c++/9/cstring:42,
                 from /llvm-project/llvm/include/llvm/ADT/Hashing.h:53,
                 from /llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
                 from /llvm-project/llvm/include/llvm/MC/MCAsmBackend.h:12,
                 from /llvm-project/llvm/lib/MC/XCOFFObjectWriter.cpp:14:
In function ‘char* strncpy(char*, const char*, size_t)’,
    inlined from ‘{anonymous}::Section::Section(const char*, llvm::XCOFF::SectionTypeFlags, bool, {anonymous}::CsectGroups)’ at /llvm-project/llvm/lib/MC/XCOFFObjectWriter.cpp:146:12:
/usr/include/x86_64-linux-gnu/bits/string_fortified.h:106:34: warning: ‘char* __builtin_strncpy(char*, const char*, long unsigned int)’ specified bound 8 equals destination size [-Wstringop-truncation]
  106 |   return __builtin___strncpy_chk (__dest, __src, __len, __bos (__dest));
      |          ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D94872
2021-01-19 14:07:11 +08:00
Lang Hames
af4971c5fa [ORC] Move OrcError.h to include/llvm/ExecutionEngine/Orc/Shared.
OrcShared is the correct home for this header since Orc was split in
1d0676b54c4. (It should have been moved in that commit, but was overlooked).
2021-01-19 16:18:00 +11:00
Luo, Yuanke
7130736d3f [X86][AMX] Clear AMX lit test case.
Add nounwind attribute to avoid generating cfi instructions. Also make
global buffer 64 bytes align in lit test case.

Differential Revision: https://reviews.llvm.org/D94910
2021-01-19 11:25:44 +08:00
Nemanja Ivanovic
b4252224e7 [PowerPC] Sign extend comparison operand for signed atomic comparisons
As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded
operand for signed subword comparisons. However, the assumption that the other
operand is correctly sign extended doesn't always hold. This patch sign extends
the other operand if it needs to be sign extended.

This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451

Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:25 -06:00
Luo, Yuanke
414d93201a [X86] Fix tile spill merge issue.
This is a additional bug fix for c5be0e0cc0. The distance for
the spill instructions is wrong in previous patch.

Differential Revision: https://reviews.llvm.org/D94772
2021-01-19 10:51:42 +08:00
Chen Zheng
7478f56eb6 Revert "[NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike."
This reverts commit 3bdf4507b66348ad78df4655a8e4f36c3fc10f3c.

Post commit comments need to be addressed first.
2021-01-18 21:33:31 -05:00
Juneyoung Lee
bdb5a6a078 Address unused variable warning 2021-01-19 09:30:16 +09:00
Juneyoung Lee
2da6d2b52c [InstCombine,InstSimplify] Optimize select followed by and/or/xor
This patch adds `A & (A && B)` -> `A && B`  (similarly for or + logical or)

Also, this patch adds `~(select C, (icmp pred X, Y), const)` -> `select C, (icmp pred' X, Y), ~const`.

Alive2 proof:
merge_and: https://alive2.llvm.org/ce/z/teMR97
merge_or: https://alive2.llvm.org/ce/z/b4yZUp
xor_and: https://alive2.llvm.org/ce/z/_-TXHi
xor_or: https://alive2.llvm.org/ce/z/2uYx_a

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94861
2021-01-19 09:14:17 +09:00
Juneyoung Lee
4eecf71ae1 [SimplifyCFG] Update SimplifyBranchOnICmpChain to recognize select form of and/or
This patch teaches SimplifyCFG::SimplifyBranchOnICmpChain to understand select form of
(x == C1 || x == C2 || ...) / (x != C1 && x != C2 && ...) and optimize them into switch if possible.
D93065 has more context about the transition, including links to the list of optimizations being updated.

Differential Revision: https://reviews.llvm.org/D93943
2021-01-19 08:53:40 +09:00
Kazu Hirata
57cbbdd64e [LoopInfo] Fix a typo in compareLoops
The code here is checking to see if two sets are identical.
OtherBlocksSet should point to OtherL->getBlocksSet() instead.

Differential Revision: https://reviews.llvm.org/D94926
2021-01-18 14:53:22 -08:00
Sanjay Patel
078c026353 [x86] add cast to avoid compile-time warning; NFC 2021-01-18 17:47:04 -05:00
Sanjay Patel
c2b5b41b35 [SLP] match maxnum/minnum intrinsics as FP reduction ops
After much refactoring over the last 2 weeks to the reduction
matching code, I think this change is finally ready.

We effectively broke fmax/fmin vector reduction optimization
when we started canonicalizing to intrinsics in instcombine,
so this should restore that functionality for SLP.

There are still FMF problems here as noted in the code comments,
but we should be avoiding miscompiles on those for fmax/fmin by
restricting to full 'fast' ops (negative tests are included).

Fixing FMF propagation is a planned follow-up.

Differential Revision: https://reviews.llvm.org/D94913
2021-01-18 17:37:16 -05:00
Craig Topper
d553b5f6af [RISCV] Remove empty Sched instantiations from the end of InstAlias defs. NFCI
InstAliases don't need scheduling information so I'm not sure what
these lines were even doing. Especially since the records don't
have names.
2021-01-18 14:08:29 -08:00
Nikita Popov
05f260b43f [PredicateInfo] Add more and/or tests (NFC) 2021-01-18 22:15:35 +01:00
Craig Topper
9e854071e5 Recommit "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."
This recommits 2c51bef76cbf0149101b9e7c7c658b4a58657929.

I've fixed the broken check line from when I renamed the test function.

Original commit message:
This builds on D94142 where scalable vectors are allowed in structs.

I did have to fix one scalable vector issue in the vector type
creation for these intrinsics where we used getVectorNumElements
instead of ElementCount.
2021-01-18 11:08:28 -08:00
Craig Topper
4299f44938 Revert "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."
This reverts commit 2c51bef76cbf0149101b9e7c7c658b4a58657929.

I seem to have messed up the check lines in the test.
2021-01-18 11:00:20 -08:00
Craig Topper
7410032174 [RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results.
This builds on D94142 where scalable vectors are allowed in structs.

I did have to fix one scalable vector issue in the vector type
creation for these intrinsics where we used getVectorNumElements
instead of ElementCount.

Differential Revision: https://reviews.llvm.org/D94149
2021-01-18 10:41:36 -08:00