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Author SHA1 Message Date
Keno Fischer
c568d201c5 [GlobalObject] Fix setSection("") 
Summary:
In rL291613, the section name was interned in LLVMContext. However,
this broke the ability to remove the section from a GlobalObject,
because it tried to intern empty strings, which is not allowed.
Fix that and add an appropriate regression test.

Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D29795

llvm-svn: 295238
 2017-02-15 21:42:42 +00:00
Sanjay Patel
5dc8de15ec [InstCombine] improve formatting; NFC 
llvm-svn: 295237
 2017-02-15 21:31:34 +00:00
Peter Collingbourne
fccb6e3a69 AssumptionCache: Disable the verifier by default, move it behind a hidden cl::opt and verify from releaseMemory(). 
This is a short term solution to the problem that many passes currently fail
to update the assumption cache. In the long term the verifier should not
be controllable with a flag. We should either fix all passes to correctly
update the assumption cache and enable the verifier unconditionally or
somehow arrange for the assumption list to be updated automatically by passes.

Differential Revision: https://reviews.llvm.org/D30003

llvm-svn: 295236
 2017-02-15 21:10:09 +00:00
Simon Pilgrim
9fc30279d8 [X86][SSE] Don't call EltsFromConsecutiveLoads if any element is missing. 
Minor performance speedup - if any call to getShuffleScalarElt fails to get a result, don't both calling for the remaining elements as EltsFromConsecutiveLoads will fail anyhow.

llvm-svn: 295235
 2017-02-15 21:09:00 +00:00
Arnold Schwaighofer
8e9cd89822 AddressSanitizer: don't track swifterror memory addresses 
They are register promoted by ISel and so it makes no sense to treat them as
memory.

Inserting calls to the thread sanitizer would also generate invalid IR.

You would hit:

"swifterror value can only be loaded and stored from, or as a swifterror
argument!"

llvm-svn: 295230
 2017-02-15 20:43:43 +00:00
Ahmed Bougacha
6d1de4abe7 [AArch64] Make am_ldrlit an iPTR - not OtherVT - operand. NFC-ish. 
am_ldrlit diverged from am_brcond in r207105, but kept the OtherVT
operand type.  It made sense for branch targets, as those are
represented as MVT::Other in SDAG.  But loads operate on pointers.

This shouldn't have an observable effect on any in-tree code, but helps
make the patterns consistent for external users.

llvm-svn: 295229
 2017-02-15 20:38:31 +00:00
Ahmed Bougacha
b0c2ac7a60 [OptDiag] Pass const Values/Types to Argument. NFC. 
llvm-svn: 295228
 2017-02-15 20:38:28 +00:00
Ahmed Bougacha
233dd4cec3 [IR] Accept 'const Type &' in the Type operator<<. NFC. 
Type::print is const; there's no reason for the operator not to be.

llvm-svn: 295227
 2017-02-15 20:38:22 +00:00
Tobias Edler von Koch
fddccdb0f9 [LTO] Add ability to emit assembly to new LTO API 
Summary:
Add a field to LTO::Config, CGFileType, to select the file type to emit (object
or assembly). This is useful for testing and to implement -save-temps.

Reviewers: tejohnson, mehdi_amini, pcc

Reviewed By: mehdi_amini

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D29475

llvm-svn: 295226
 2017-02-15 20:36:36 +00:00
Kyle Butt
96c1e7e4f0 Codegen: Make chains from trellis-shaped CFGs 
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:

  A     B
  |\   /|
  | \ / |
  |  X  |
  | / \ |
  |/   \|
  C     D

would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.

because of this we can tail duplicate to extend existing trellises.

As an example consider the following CFG:

    B   D   F   H
   / \ / \ / \ / \
  A---C---E---G---Ret

Where A,C,E,G are all small (Currently 2 instructions).

The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.

The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret

define void @straight_test(i32 %tag) {
entry:
  br label %test1
test1: ; A
  %tagbit1 = and i32 %tag, 1
  %tagbit1eq0 = icmp eq i32 %tagbit1, 0
  br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
  call void @a()
  br label %test2
test2: ; C
  %tagbit2 = and i32 %tag, 2
  %tagbit2eq0 = icmp eq i32 %tagbit2, 0
  br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
  call void @b()
  br label %test3
test3: ; E
  %tagbit3 = and i32 %tag, 4
  %tagbit3eq0 = icmp eq i32 %tagbit3, 0
  br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
  call void @c()
  br label %test4
test4: ; G
  %tagbit4 = and i32 %tag, 8
  %tagbit4eq0 = icmp eq i32 %tagbit4, 0
  br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
  call void @d()
  br label %exit
exit:
  ret void
}

here is the layout after D27742:
straight_test:                          # @straight_test
; ... Prologue elided
; BB#0:                                 # %entry ; A (merged with test1)
; ... More prologue elided
	mr 30, 3
	andi. 3, 30, 1
	bc 12, 1, .LBB0_2
; BB#1:                                 # %test2 ; C
	rlwinm. 3, 30, 0, 30, 30
	beq	 0, .LBB0_3
	b .LBB0_4
.LBB0_2:                                # %optional1 ; B (copy of C)
	bl a
	nop
	rlwinm. 3, 30, 0, 30, 30
	bne	 0, .LBB0_4
.LBB0_3:                                # %test3 ; E
	rlwinm. 3, 30, 0, 29, 29
	beq	 0, .LBB0_5
	b .LBB0_6
.LBB0_4:                                # %optional2 ; D (copy of E)
	bl b
	nop
	rlwinm. 3, 30, 0, 29, 29
	bne	 0, .LBB0_6
.LBB0_5:                                # %test4 ; G
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
	b .LBB0_7
.LBB0_6:                                # %optional3 ; F (copy of G)
	bl c
	nop
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
.LBB0_7:                                # %optional4 ; H
	bl d
	nop
.LBB0_8:                                # %exit ; Ret
	ld 30, 96(1)                    # 8-byte Folded Reload
	addi 1, 1, 112
	ld 0, 16(1)
	mtlr 0
	blr

The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.

This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.

Here is the resulting concrete layout:

straight_test:                          # @straight_test
; BB#0:                                 # %entry ; A (merged with test1)
	mr 30, 3
	andi. 3, 30, 1
	bc 12, 1, .LBB0_4
; BB#1:                                 # %test2 ; C
	rlwinm. 3, 30, 0, 30, 30
	bne	 0, .LBB0_5
.LBB0_2:                                # %test3 ; E
	rlwinm. 3, 30, 0, 29, 29
	bne	 0, .LBB0_6
.LBB0_3:                                # %test4 ; G
	rlwinm. 3, 30, 0, 28, 28
	bne	 0, .LBB0_7
	b .LBB0_8
.LBB0_4:                                # %optional1 ; B (Copy of C)
	bl a
	nop
	rlwinm. 3, 30, 0, 30, 30
	beq	 0, .LBB0_2
.LBB0_5:                                # %optional2 ; D (Copy of E)
	bl b
	nop
	rlwinm. 3, 30, 0, 29, 29
	beq	 0, .LBB0_3
.LBB0_6:                                # %optional3 ; F (Copy of G)
	bl c
	nop
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
.LBB0_7:                                # %optional4 ; H
	bl d
	nop
.LBB0_8:                                # %exit

Differential Revision: https://reviews.llvm.org/D28522

llvm-svn: 295223
 2017-02-15 19:49:14 +00:00
Xinliang David Li
06359df83c include function name in dot filename 
Differential Revision: http://reviews.llvm.org/D29975

llvm-svn: 295220
 2017-02-15 19:21:04 +00:00
Arnold Schwaighofer
d83716804c ThreadSanitizer: don't track swifterror memory addresses 
They are register promoted by ISel and so it makes no sense to treat them as
memory.

Inserting calls to the thread sanitizer would also generate invalid IR.

You would hit:

"swifterror value can only be loaded and stored from, or as a swifterror
argument!"

llvm-svn: 295215
 2017-02-15 18:57:06 +00:00
Michael Kuperstein
8c57546852 [DAG] Don't try to create an INSERT_SUBVECTOR with an illegal source 
We currently can't legalize those, but we should really not be creating
them in the first place, since legalization would probably look similar to the
way we legalize CONCAT_VECTORS - basically replace the INSERT with a BUILD.

This fixes PR311956.

Differential Revision: https://reviews.llvm.org/D29961

llvm-svn: 295213
 2017-02-15 18:37:26 +00:00
Dehao Chen
ca296c6427 Expose getBaseDiscriminatorFromDiscriminator, getDuplicationFactorFromDiscriminator and getCopyIdentifierFromDiscriminator API so that downstream tools can use them to get the correct encoding. 
Summary: Discriminators are now encoded with rich information. This patch exposes the encoding API to downstream tools.

Reviewers: davidxl, hfinkel

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29852

llvm-svn: 295210
 2017-02-15 17:54:39 +00:00
Sanjay Patel
3d1a3c399b [Inline] add tests to show attribute information loss; NFC 
llvm-svn: 295209
 2017-02-15 17:42:58 +00:00
Simon Pilgrim
34646fef86 [X86][SSE] Propagate undef upper elements from scalar_to_vector during shuffle combining 
Only do this for integer types currently - floats types (in particular insertps) load folding often fails with this.

llvm-svn: 295208
 2017-02-15 17:41:33 +00:00
Stanislav Mekhanoshin
b83595fd3c [AMDGPU] Revert failed scheduling 
This patch reverts region's scheduling to the original untouched state
in case if we have have decreased occupancy.

In addition it switches to use TargetRegisterInfo occupancy callback
for pressure limits instead of gradually increasing limits which were
just passed by. We are going to stay with the best schedule so we do
not need to tolerate worsened scheduling anymore.

Differential Revision: https://reviews.llvm.org/D29971

llvm-svn: 295206
 2017-02-15 17:19:50 +00:00
Anna Thomas
08063ea857 Revert "[JumpThreading] Thread through guards" 
This reverts commit r294617.

We fail on an assert while trying to get a condition from an
unconditional branch.

llvm-svn: 295200
 2017-02-15 17:08:29 +00:00
Simon Pilgrim
5bc87e6237 [X86] Regenerate scalar stack reload test 
llvm-svn: 295195
 2017-02-15 16:48:45 +00:00
David Bozier
68899b4bb1 Fix unittest for buildbot with mips host (32bit big endian) from r295174 
llvm-svn: 295188
 2017-02-15 16:03:22 +00:00
Sanjay Patel
e262bb4f6a [InlineFunction] use getFunction(); NFC 
llvm-svn: 295185
 2017-02-15 15:22:18 +00:00
Simon Pilgrim
e3f91a8e7e Fix spelling mistake - paramater -> parameter. NFCI. 
llvm-svn: 295182
 2017-02-15 15:11:36 +00:00
Sanjay Patel
ed8f4cd386 [InlineFunction] use getCaller(); NFCI 
llvm-svn: 295181
 2017-02-15 15:08:38 +00:00
Sanjay Patel
9a7c30ca60 [InlineFunction] use range-for loop; NFCI 
llvm-svn: 295179
 2017-02-15 14:56:11 +00:00
Simon Pilgrim
7b99551942 [X86] Regenerate i64 ext-load on 32-bit target tests 
llvm-svn: 295177
 2017-02-15 14:06:17 +00:00
David Bozier
e2cb5e4c4d Attempt to fix buildbots after commit of r295173. 
Unit tests needed to check on the endianness of the host platform. (Test was failing for big endian hosts).

llvm-svn: 295174
 2017-02-15 13:40:05 +00:00
David Bozier
8404150bcd Fix incorrect formatting of DataRefImpl members in operator<< function 
Changed format specifiers to use format macro constant for pointer type. 
Moved width part of format specifier in the correct place for formatting members a and b.

Added a unit test to confirm the output.

Differential Revision: https://reviews.llvm.org/D28957

llvm-svn: 295173
 2017-02-15 12:58:41 +00:00
Simon Pilgrim
d72380da07 [X86][SSE] Allow matchVectorShuffleWithUNPCK to recognise ZERO inputs 
Add support for specifying an UNPCK input as ZERO, particularly improves ZEXT cases with non-zero offsets

llvm-svn: 295169
 2017-02-15 11:46:15 +00:00
Sagar Thakur
5602c70c9c [LLVM][XRAY][MIPS] Support xray on mips/mipsel/mips64/mips64el 
Summary: Adds support for xray instrumentation on mips for both 32-bit and 64-bit.

Reviewed by sdardis, dberris
Differential: D27697

llvm-svn: 295164
 2017-02-15 10:48:11 +00:00
Daniel Jasper
e27f967c5e Revert r295110 and r295144. 
This fails under ASAN:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/798/steps/check-llvm%20asan/logs/stdio

llvm-svn: 295162
 2017-02-15 09:56:08 +00:00
Ayman Musa
0d84646f4f [X86][AVX] Remove REX_W from AVX instructions. 
There is no meaning for REX_W in VEX encoded AVX instruction.

Differential Revision: https://reviews.llvm.org/D29894

llvm-svn: 295157
 2017-02-15 08:12:16 +00:00
Craig Topper
76be63ff7e [X86] Don't create VBROADCAST nodes with 256-bit or 512-bit input types 
Summary:
We don't seem to have great rules on what a valid VBROADCAST node looks like. And as a consequence we end up with a lot of patterns to try to catch everything. We have patterns with scalar inputs, 128-bit vector inputs, 256-bit vector inputs, and 512-bit vector inputs.

As you can see from the things improved here we are currently missing patterns for 128-bit loads being extended to 256-bit before the vbroadcast.

I'd like to propose that VBROADCAST should always take a 128-bit vector type as input. As a first step towards that this patch adds an EXTRACT_SUBVECTOR in front of VBROADCAST when the input is 256 or 512-bits. In the future I would like to add scalar_to_vector around all the scalar operations. And maybe we should consider adding a VBROADCAST+load node to avoid separating loads from the broadcasting operation when the load itself isn't foldable.

This requires an additional change in target shuffle combining to look for the extract subvector and look through it to find the original operand. I'm sure this change isn't perfect but was enough to fix a few test failures that were being caused.

Another interesting thing I noticed is that the changes in masked_gather_scatter.ll show cases were we don't remove a useless insert into element 1 before broadcasting element 0.

Reviewers: delena, RKSimon, zvi

Reviewed By: zvi

Subscribers: igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D28747

llvm-svn: 295155
 2017-02-15 06:58:47 +00:00
Craig Topper
3bb487333f [AVX-512] Add PACKSS/PACKUS instructions to load folding tables. 
llvm-svn: 295154
 2017-02-15 06:51:39 +00:00
Craig Topper
a77b0bd57e [SelectionDAGBuilder] Simplify creation of shufflevector DAG nodes where inputs are larger than the mask 
Summary:
The current code loops over all elements to calculate a used range. Then a second short loop looks at the ranges and determines if they can be used in a extract and creates a properly aligned start index for the extract.

This range finding is unnecessary, we can just calculate a properly aligned start index for an extract for each input during the first loop. If we don't find the same start index for each indice we can't use an extract.

Reviewers: zvi, RKSimon

Reviewed By: zvi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29926

llvm-svn: 295152
 2017-02-15 05:57:16 +00:00
Lang Hames
7d65fb66f1 [Orc][RPC] Add a AsyncHandlerTraits specialization for non-value-type response 
handler args.

The specialization just inherits from the std::decay'd response handler type.
This allows member functions (via MemberFunctionWrapper) to be used as async
handlers.

llvm-svn: 295151
 2017-02-15 05:39:35 +00:00
Peter Collingbourne
8facf0faed AssumptionCache: Update documentation comment. 
The comment was somewhat misleading in that it implied that passes were not
responsible for adding new assumptions to the assumption cache. This new
wording now explicitly mentions that they are required to do so.

Differential Revision: https://reviews.llvm.org/D29977

llvm-svn: 295148
 2017-02-15 03:50:01 +00:00
Peter Collingbourne
67e37dae1a SimplifyCFG: Register cloned assume intrinsics with assumption cache when creating critical edge. 
Differential Revision: https://reviews.llvm.org/D29976

llvm-svn: 295145
 2017-02-15 03:01:11 +00:00
Peter Collingbourne
2d43a970d9 WholeProgramDevirt: Separate the code that applies optzns from the code that decides whether to apply them. NFCI. 
The idea is that the apply* functions will also be called when importing
devirt optimizations.

Differential Revision: https://reviews.llvm.org/D29745

llvm-svn: 295144
 2017-02-15 02:13:08 +00:00
Rui Ueyama
37d92ea7e3 Revert r295138: Instead of a series of string operations, use snprintf(). 
This broke buildbots.

llvm-svn: 295142
 2017-02-15 01:48:33 +00:00
Rui Ueyama
c5259de55d Instead of a series of string operations, use snprintf(). 
llvm-svn: 295138
 2017-02-15 01:09:40 +00:00
Rui Ueyama
4a53068a32 Return early. NFC. 
llvm-svn: 295137
 2017-02-15 01:09:20 +00:00
Rui Ueyama
523b3609bd Use LLVM-style naming scheme. 
llvm-svn: 295136
 2017-02-15 01:09:01 +00:00
Stanislav Mekhanoshin
479d45f82d [AMDGPU] Fix MaxWorkGroupsPerCU for large workgroups 
This patch corrects the maximum workgroups per CU if we have big
workgroups (more than 128). This calculation contributes to the
occupancy calculation in respect to LDS size.

Differential Revision: https://reviews.llvm.org/D29974

llvm-svn: 295134
 2017-02-15 01:03:59 +00:00
Rui Ueyama
14aaabfcef Use LLVM-style naming scheme. 
llvm-svn: 295132
 2017-02-15 00:28:48 +00:00
Rui Ueyama
e3b1fc3c3c Remove useless local variable. 
llvm-svn: 295131
 2017-02-15 00:28:26 +00:00
Rui Ueyama
48672807eb Split WinCOFFObjectWriter::defineSection. NFC. 
llvm-svn: 295128
 2017-02-15 00:15:54 +00:00
Rui Ueyama
b2f6511e57 Simplify WinCOFFObjectWriter by removing a template member function. 
llvm-svn: 295126
 2017-02-14 23:58:19 +00:00
Rui Ueyama
e3d0caed95 Do not lookup a DenseMap twice using the same key. 
llvm-svn: 295124
 2017-02-14 23:47:34 +00:00
Rui Ueyama
2ae5f34223 Use endian::write32le instead of endian::write. 
llvm-svn: 295120
 2017-02-14 23:28:19 +00:00
Rui Ueyama
2e6de99b22 Use zero-initialization instead of memset. 
llvm-svn: 295119
 2017-02-14 23:28:01 +00:00