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Commit Graph

176307 Commits

Author SHA1 Message Date
Jessica Paquette
9a354720e0 [AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.

Also better code-reuse, etc., etc.

Differential Revision: https://reviews.llvm.org/D59323

llvm-svn: 356107
2019-03-13 23:29:54 +00:00
Jessica Paquette
4117eab6b5 [GlobalISel][AArch64] Gardening: Factor out vector inserts
Factor out the vector insert code in `selectBuildVector`. Replace part of it
with `emitScalarToVector`, since it was pretty much equivalent.

This will make implementing G_INSERT_VECTOR_ELT easier.

Differential Revision: https://reviews.llvm.org/D59322

llvm-svn: 356106
2019-03-13 23:22:23 +00:00
Jordan Rupprecht
bd637ddd64 [llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency
error() was previously cleaned up from CopyConfig, but new uses were introduced.

This also tweaks the error message for --add-symbol to report all invalid flags.

llvm-svn: 356105
2019-03-13 22:26:01 +00:00
Jason Liu
59e6264189 [AIX][CMake] Changes for building on AIX with XL and GCC
Summary:
In support of IBM's efforts to produce a viable C and C++ LLVM compiler for AIX
(ref: RFC at http://lists.llvm.org/pipermail/llvm-dev/2019-February/130175.html),
this patch adds customizations to the CMake files in order to properly
invoke the host toolchain for the build on AIX.
Additional changes to enable a successful build will follow.

Patch by Xing Xue

Reviewers: hubert.reinterpretcast, jasonliu, sfertile

Reviewed by: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D58250

llvm-svn: 356104
2019-03-13 21:50:25 +00:00
Sam Clegg
30ab5034f3 [WebAssembly] Improve support for "needed" list in dylink section
This change adds basic support for shared library dependencies
via the dylink section.

See https://github.com/WebAssembly/tool-conventions/pull/77

Differential Revision: https://reviews.llvm.org/D59237

llvm-svn: 356102
2019-03-13 21:29:20 +00:00
Jessica Paquette
fcc568af0c [GlobalISel][AArch64] Gardening: Factor out code to find lane indices
Some more refactoring for G_INSERT_VECTOR_ELT.

Factor out the code used to find a lane index from `selectExtractElt`. Put it
into a more general-purpose `getConstantValueForReg` function.

This will be shared with the code for G_INSERT_VECTOR_ELT.

Differential Revision: https://reviews.llvm.org/D59324

llvm-svn: 356101
2019-03-13 21:19:29 +00:00
Stanislav Mekhanoshin
0210f14ed7 [AMDGPU] Silence gcc 7 warnings
Differential Revision: https://reviews.llvm.org/D59330

llvm-svn: 356100
2019-03-13 21:15:52 +00:00
Matt Arsenault
edde3c0772 Verifier: Make sure masked load/store alignment is a power of 2
The same should also be done for scatter/gather, but the verifier
doesn't check those at all now.

llvm-svn: 356094
2019-03-13 19:46:34 +00:00
Matt Arsenault
4715acf963 PowerPC: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356093
2019-03-13 19:46:34 +00:00
Matt Arsenault
df1b94ab2b Hexagon: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356092
2019-03-13 19:46:33 +00:00
Matt Arsenault
e4cca33438 SystemZ: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356091
2019-03-13 19:46:32 +00:00
Matt Arsenault
4fd9f27be3 Mips: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

I'm not sure what's going on with the immediates.ll test. It seems to
be intended to test invalid cases like this, but then tries to handle
some of them anyway. I've moved the cases that were inconsistent with
the GCCBuiltin definition so they don't test the codegen anymore.

llvm-svn: 356085
2019-03-13 19:07:59 +00:00
Simon Pilgrim
62e4fd4760 [X86] Remove icmp undef in more reduced tests
llvm-svn: 356084
2019-03-13 19:07:54 +00:00
Simon Pilgrim
68220b2059 [X86] Regenerate tail call tests
llvm-svn: 356083
2019-03-13 19:04:45 +00:00
Tim Renouf
c1e384ffaa [MsgPack] Removed MsgPackTypes
Summary:
MsgPackTypes has been replaced by the lighter-weight MsgPackDocument.

Differential Revision: https://reviews.llvm.org/D57025

Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4
llvm-svn: 356082
2019-03-13 18:56:33 +00:00
Tim Renouf
0740b7d5b8 [AMDGPU] Switched HSA metadata to use MsgPackDocument
Summary:
MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This
commit switches AMDGPU HSA metadata processing to use MsgPackDocument
instead of MsgPackTypes.

Differential Revision: https://reviews.llvm.org/D57024

Change-Id: I0751668013abe8c87db01db1170831a76079b3a6
llvm-svn: 356081
2019-03-13 18:55:50 +00:00
Tim Renouf
2600aff087 [MsgPack] New MsgPackDocument class
Summary:
A class that exposes a simple in-memory representation of a document of
MsgPack objects, that can be read from and written to MsgPack, read from
and written to YAML, and inspected and modified in memory. This is
intended to be a lighter-weight (in terms of memory allocations)
replacement for MsgPackTypes.

Two subsequent changes will:
1. switch AMDGPU HSA metadata to using MsgPackDocument instead of
   MsgPackTypes;
2. add MsgPack AMDGPU PAL metadata via MsgPackDocument.

Differential Revision: https://reviews.llvm.org/D57023

Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1
llvm-svn: 356080
2019-03-13 18:54:47 +00:00
Craig Topper
53b1ed4a97 [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.

We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.

I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.

Differential Revision: https://reviews.llvm.org/D59308

llvm-svn: 356078
2019-03-13 18:48:50 +00:00
Simon Pilgrim
062a2c49e3 [X86] Avoid icmp undef in reduced tests
Because we don't currently simplify icmp with undef in DAG, bugpoint loves to introduce them during reduction.

This is a small step towards re-adding non-undef values into some of the simpler tests so that they should still test correctly and emit similar/same codegen.

Prep work for PR40800 ([SelectionDAG] Add UNDEF handling to SelectionDAG::FoldSetCC).

llvm-svn: 356076
2019-03-13 18:36:59 +00:00
Alex Bradbury
c2d8f64443 [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to
reflect this, and remove the NOLIB check lines (they're redundant given that
the RV32I and RV64I check lines generated by update_llc_test_checks.py already
demonstrate there is no libcall).

llvm-svn: 356074
2019-03-13 18:25:23 +00:00
Simon Pilgrim
4c49e09099 Regenerate test
llvm-svn: 356071
2019-03-13 18:18:24 +00:00
Nirav Dave
3f1952d8de [DAGCombiner] Fix Comment. NFC.
llvm-svn: 356069
2019-03-13 17:44:40 +00:00
Nirav Dave
6655b5e078 [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.

Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.

CodeGen tests with non-reordering changes:

  X86/aligned-variadic.ll -- memory-based add folded into stored leaq
  value.

  X86/constant-combiners.ll -- Optimizes out overlap between stores.

  X86/pr40631_deadstore_elision -- folds constant byte store into
  preceding quad word constant store.

Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet

Reviewed By: courbet

Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59260

llvm-svn: 356068
2019-03-13 17:07:09 +00:00
Simon Pilgrim
268ff3b066 [X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode
llvm-svn: 356067
2019-03-13 17:00:18 +00:00
Simon Pilgrim
cbbfb5ea0e [X86][AVX] Add combineConcatVectors support to improve subvector handling
Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization.

This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time.

The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit.

llvm-svn: 356064
2019-03-13 16:37:30 +00:00
Alex Bradbury
a678d607a6 [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.

llvm-svn: 356063
2019-03-13 16:33:45 +00:00
Alex Bradbury
262a0524ce [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s
Note that s0 need not be marked reserved if the frame pointer isn't used. For
the ILP32 and LP64 soft float ABIS that are currently support, all FPRs are
always considered temporaries.

llvm-svn: 356061
2019-03-13 16:14:16 +00:00
Simon Atanasyan
27f5465731 [mips] Join some adjacent let DecoderNamespace blocks. NFC
llvm-svn: 356059
2019-03-13 16:00:42 +00:00
Louis Dionne
638bfc7d2a [NFC][CMake] Improve Status message in the iOS toolchain file
llvm-svn: 356056
2019-03-13 15:35:21 +00:00
Sander de Smalen
7504579c30 [AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
This test is added to see difference created by:

  https://reviews.llvm.org/D59259

llvm-svn: 356054
2019-03-13 15:18:27 +00:00
Sanjay Patel
996b4d3924 [x86] limit extractelement of setcc to pre-legalization
A fuzzer found the crasher:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13700

The bug was introduced recently here:
rL355741

This is the quick fix. If we need to do this transform
later, then we'd have to extend/truncate the vector setcc
element type to the scalar setcc type (i8). 

llvm-svn: 356053
2019-03-13 14:49:52 +00:00
Simon Atanasyan
e4c4aa3874 [mips] Fix encoding of the mov.d command for microMIPS R6
Before this change LLVM emits non-microMIPS variant of the `mov.d`
command for microMIPS code.

Differential Revision: http://reviews.llvm.org/D59045

llvm-svn: 356052
2019-03-13 14:23:12 +00:00
Simon Atanasyan
97f0b70b96 [mips] Define mov.d instructions using ABSS_M multiclass. NFC
llvm-svn: 356051
2019-03-13 14:22:58 +00:00
Clement Courbet
b854c089a3 Re-land r354244 "[DAGCombiner] Eliminate dead stores to stack."
Always check candidates for hasOtherUses(), not only stores.

llvm-svn: 356050
2019-03-13 13:56:23 +00:00
Simon Pilgrim
f505cb7adc Fix signed/unsigned mismatch warning. NFCI.
llvm-svn: 356046
2019-03-13 13:14:14 +00:00
Simon Atanasyan
b8ca8b155a [mips] Map SW instruction to its microMIPS R6 variant
To provide mapping between standard and microMIPS R6 variants of the
`sw` command we have to rename SWSP_xxx commands from "sw" to "swsp".
Otherwise `tablegen` starts to show the error `Multiple matches found
for `SW'`. After that to restore printing SWSP command as `sw`, I add
an appropriate `MipsInstAlias` instance.

We also need to implement "size reduction" for microMIPS R6. But this
task is for separate patch. After that the `micromips-lwsp-swsp.ll` test
case will be extended.

Differential Revision: http://reviews.llvm.org/D59046

llvm-svn: 356045
2019-03-13 13:09:30 +00:00
Alex Bradbury
715a62d0ab [RISCV] Regenerate umulo-128-legalisation-lowering.ll
Upstream changes have improved codegen, reducing stack usage. Regenerate the test.

llvm-svn: 356044
2019-03-13 12:33:44 +00:00
Simon Pilgrim
ac6f6352c9 [X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcasts
AVX1 broadcasts were failing as we were adding bitcasts that caused MayFoldLoad's hasOneUse to return false.

This patch stops introducing bitcasts so early and also replaces the broadcast index scaling through bitcasts (which can't succeed in some cases) to instead just keep track of the bitoffset which can be converted back to the broadcast index later on.

Differential Revision: https://reviews.llvm.org/D58888

llvm-svn: 356043
2019-03-13 12:20:39 +00:00
Simon Pilgrim
76bc7292cf Appease MSVC builds by #ifdef wrapping runAndGetCommandOutput tests. NFCI.
llvm-svn: 356042
2019-03-13 11:51:13 +00:00
Jeremy Morse
32ca0e55db [DebugInfo][Docs] Document how dbg.value intrinsics are interpreted in optimized code
This patch adds a section, ``Object lifetime in optimized code'', that
documents how such intrinsics are supposed to be handled. It sets out some of
the principles of how they specify variable locations, and how long those
locations are valid for.

This patch also documents one of the objectives behind the variable-location
design, that we should never allow the debugger to observe a state of the
program that would not have appeared without optimization.

Differential Revision: https://reviews.llvm.org/D58726

llvm-svn: 356041
2019-03-13 11:43:13 +00:00
Simon Pilgrim
6219680ed0 [DAG] Move integer setcc %x, %x folding into FoldSetCC
First step towards PR40800 - I intend to move the float case in a separate future patch.

I had to tweak the (overly reduced) thumb2 test and the x86 widening test change is annoying (no longer rematerializable) but we should address this separately.

Differential Revision: https://reviews.llvm.org/D59244

llvm-svn: 356040
2019-03-13 11:08:57 +00:00
Simon Atanasyan
19e953f0bb [MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansion
On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless
of +dsp argument. This patch checks is HasDSP predicate is present for
PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate.

Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair.

Patch by Mirko Brkusanin.

Differential Revision: http://reviews.llvm.org/D59203

llvm-svn: 356039
2019-03-13 11:04:38 +00:00
Simon Atanasyan
30d72c77b6 [mips] Fix CPU used in the test case to suppress warning. NFC
The MSA ASE used in in the test case requires MIPS32 revision 5 or
greater while the test uses MIPS32 revision 1.

llvm-svn: 356038
2019-03-13 11:04:28 +00:00
Jonas Hahnfeld
d1e932f9c7 [ELF] Fix GCC8 warnings about "fall through", NFCI
Add break statements in Object/ELF.cpp since the code should consider the
generic tags for Hexagon, MIPS, and PPC. Add a test (copied from llvm-readobj)
to show that this works correctly (earlier versions of this patch would have
asserted).

The warnings in X86ELFObjectWriter.cpp are actually false-positives since
the nested switch() handles all possible values and returns in all cases.
Make this explicit by adding llvm_unreachable's.

Differential Revision: https://reviews.llvm.org/D58837

llvm-svn: 356037
2019-03-13 10:38:17 +00:00
Jonas Hahnfeld
43533d9532 [Support] Treat truncation of fullpath as error
If the concatenation of arguments dir and bin has at least PATH_MAX
characters the call to snprintf will truncate. The result will usually
not exist, but if it does it's actually incorrect to return that the
path exists.
(Motivated by GCC compiler warning about format truncation.)

Differential Revision: https://reviews.llvm.org/D58835

llvm-svn: 356036
2019-03-13 10:37:56 +00:00
Alex Bradbury
ba45169928 [RISCV] Replace incorrect use of sizeof with array_lengthof
RISCVDisassembler was incorrectly using sizeof(Arr) when it should have used
sizeof(Arr)/sizeof(Arr[0]). Update to use array_lengthof instead.

llvm-svn: 356035
2019-03-13 09:22:57 +00:00
Paul Hoad
08fd1ff105 Revert "[clang-format] [PR25010] AllowShortIfStatementsOnASingleLine not working if an "else" statement is present"
This reverts commit b358cbb9b78389e20f7be36e1a98e26515c3ecce.

llvm-svn: 356030
2019-03-13 08:15:03 +00:00
Paul Hoad
bb64ce3b63 [clang-format] [PR25010] AllowShortIfStatementsOnASingleLine not working if an "else" statement is present
Summary:
Addressing: PR25010 - https://bugs.llvm.org/show_bug.cgi?id=25010

Code like:

```
    if(true) var++;
    else  {
        var--;
    }
```

is reformatted to be

```
  if (true)
    var++;
  else {
    var--;
  }
```

Even when `AllowShortIfStatementsOnASingleLine` is true

The following revision comes from a +1'd suggestion in the PR to support AllowShortIfElseStatementsOnASingleLine

This suppresses the clause prevents the merging of the if when there is a compound else

Reviewers: klimek, djasper, JonasToth, alexfh, krasimir, reuk
Reviewed By: reuk
Subscribers: reuk, Higuoxing, jdoerfert, cfe-commits
Tags: #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D59087

llvm-svn: 356029
2019-03-13 08:07:46 +00:00
Philip Reames
93ee9eff73 [ImplicitNullChecks] Support unordered atomic accesses
Update the INC pass to allow folding unordered atomics.  This is the first optimization unblocked by the changes landed from D57601.

llvm-svn: 356006
2019-03-13 03:25:20 +00:00
Philip Reames
c25531527b [Tests] Expand implicit null check coverage
llvm-svn: 356004
2019-03-13 03:17:58 +00:00