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Author SHA1 Message Date
Mikhail Glushenkov
c802d57e52 Input files should go before all other options. 
Important, for example, when calling 'gcc a.o b.o c.o -lD -lE -lF'.

llvm-svn: 83524
 2009-10-08 04:40:08 +00:00
Jim Grosbach
9f57f9bee6 Cleanup up unused R3LiveIn tracking. 
llvm-svn: 83522
 2009-10-08 01:50:26 +00:00
Jim Grosbach
a3e1149941 Re-enable register scavenging in Thumb1 by default. 
llvm-svn: 83521
 2009-10-08 01:46:59 +00:00
Jim Grosbach
a8e8c8a28f bugfix. The target may use virtual registers that aren't tracked for re-use but are allocated by the scavenger. The re-use algorithm needs to watch for that. 
llvm-svn: 83519
 2009-10-08 01:09:45 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Jeffrey Yasskin
e36facef86 In instcombine's debug output, avoid printing ADD for instructions that are 
already on the worklist, and print Visited when an instruction is about to be
visited.  Net, on one input, this reduced the output size by at least 9x.

llvm-svn: 83510
 2009-10-08 00:12:24 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
c7baa2832f Convert more NEON tests to use FileCheck. 
llvm-svn: 83507
 2009-10-07 23:47:21 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Jeffrey Yasskin
0aff0ecaf1 Fix the OProfile part of PR5018. This fixes --without-oprofile, makes 
it the default, and works around a broken libopagent on some Debian
systems.

llvm-svn: 83503
 2009-10-07 23:22:42 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Jim Grosbach
cb905d28a8 reverting thumb1 scavenging default due to test failure while I figure out what's up. 
llvm-svn: 83501
 2009-10-07 22:49:41 +00:00
Chris Lattner
41e4cd7ef4 second half of lazy liveness removal. 
llvm-svn: 83500
 2009-10-07 22:49:30 +00:00
Dale Johannesen
ba62bb565d Fix handling of x86 'R' constraint. 
llvm-svn: 83499
 2009-10-07 22:47:20 +00:00
Bob Wilson
97bab9ef32 Convert more NEON tests to use FileCheck. 
llvm-svn: 83497
 2009-10-07 22:30:19 +00:00
Jim Grosbach
cc952b2ff8 Enable thumb1 register scavenging by default. 
llvm-svn: 83496
 2009-10-07 22:26:31 +00:00
Jim Grosbach
a9d83ba92c Enable thumb1 register scavenging by default. 
llvm-svn: 83494
 2009-10-07 22:26:14 +00:00
Devang Patel
a7456a1335 Extract subprogram and compile unit information from the debug info attached to an instruction. 
llvm-svn: 83491
 2009-10-07 22:04:08 +00:00
Bob Wilson
e7173601a3 Add some instruction encoding bits for NEON load/store instructions. 
llvm-svn: 83490
 2009-10-07 21:53:04 +00:00
Eric Christopher
a42e55349d 80-column and whitespace fixes. 
llvm-svn: 83489
 2009-10-07 21:14:25 +00:00
Kevin Enderby
ef201aaa04 Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" so 
that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16

llvm-svn: 83488
 2009-10-07 20:57:20 +00:00
Bob Wilson
a367eb439c Convert test to FileCheck. 
llvm-svn: 83487
 2009-10-07 20:51:42 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Jim Grosbach
0609c91ec4 grammar 
llvm-svn: 83483
 2009-10-07 19:08:36 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Jim Grosbach
5db951c6a2 add initializers for clarity. Add missing assignment of PrevLastUseOp. 
llvm-svn: 83481
 2009-10-07 18:44:24 +00:00
Owen Anderson
132727997c Remove LazyLiveness from the tree. It doesn't work right now, and I'm not going to have the time 
to finish it any time soon.  If someone's interested it, they can resurrect it from SVN history.

llvm-svn: 83480
 2009-10-07 18:40:17 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Kevin Enderby
c0d0a1ec58 Add another bit of the ARM target assembler to llvm-mc to parse registers 
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.

llvm-svn: 83477
 2009-10-07 18:01:35 +00:00
Dan Gohman
0447afe915 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and 
teach it how to recognize invariant physical registers.

llvm-svn: 83476
 2009-10-07 17:47:20 +00:00
Dan Gohman
b95136e649 Replace TargetInstrInfo::isInvariantLoad and its target-specific 
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475
 2009-10-07 17:38:06 +00:00
Dan Gohman
aa09eaa3e8 Add a few simple MachineVerifier checks for MachineMemOperands. 
llvm-svn: 83474
 2009-10-07 17:36:00 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Bob Wilson
39328dad67 Add tests for vld2 of 128-bit vectors. 
llvm-svn: 83468
 2009-10-07 17:19:13 +00:00
Jim Grosbach
61c5ce1bde Add register-reuse to frame-index register scavenging. When a target uses 
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467
 2009-10-07 17:12:56 +00:00
Devang Patel
c411175393 Do not assume that the module is set. 
llvm-svn: 83462
 2009-10-07 16:37:55 +00:00
Torok Edwin
8203691f27 Add a comment explaining how DenseMap::insert works, because it is not 
intuitive.
It does NOT update the value if the key is already in the map,
it also returns false if the key is already in the map, regardless
if the value matched.

llvm-svn: 83458
 2009-10-07 09:23:56 +00:00
Torok Edwin
6a66b4edd1 Add PR to this FIXME, looks like I didn't commit this change after all. 
llvm-svn: 83457
 2009-10-07 09:22:55 +00:00
Duncan Sands
27cb155f76 Make getPointerTo return a const PointerType* rather than 
an unqualified PointerType* because it seems more correct.

llvm-svn: 83454
 2009-10-07 07:35:19 +00:00
Dan Gohman
aab60a27fc INTRINSIC_W_CHAIN and INTRINSIC_VOID do not use MemSDNode. They 
may access memory, but they don't carry a MachineMemOperand.

llvm-svn: 83449
 2009-10-07 03:00:18 +00:00
Eric Christopher
e6bebc66a7 Add FreeInst to the "is a call" check for Insts that are calls, but 
not intrinsics.

llvm-svn: 83441
 2009-10-07 00:54:08 +00:00
Dan Gohman
564b5f75ac Fix this comment. The loop header is the loop entry point. 
llvm-svn: 83437
 2009-10-07 00:33:10 +00:00
Anton Korobeynikov
aba66ae89b Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

llvm-svn: 83435
 2009-10-07 00:06:35 +00:00
Eric Christopher
8720c9ca69 While we still have a MallocInst treat it as a call like any other 
for inlining.

When MallocInst goes away this code will be subsumed as part of
calls and work just fine...

llvm-svn: 83434
 2009-10-07 00:02:18 +00:00
Kevin Enderby
2c772c1ae9 Added bits of the ARM target assembler to llvm-mc to parse some load instruction 
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.

llvm-svn: 83424
 2009-10-06 22:26:42 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00
Bob Wilson
8c108dc476 Use copyRegToReg hook to copy registers. 
llvm-svn: 83421
 2009-10-06 22:01:15 +00:00