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Commit Graph

111884 Commits

Author SHA1 Message Date
Matt Arsenault
2f04c34f62 R600/SI: Fix trailing comma with modifiers
Instructions with 1 operand can still use source modifiers,
so make sure we don't print an extra comma afterwards.

llvm-svn: 226226
2015-01-15 23:17:03 +00:00
Colin LeMahieu
ef6291ec41 [Hexagon] Adding new-value store and bit reverse instructions.
llvm-svn: 226224
2015-01-15 23:10:29 +00:00
Filipe Cabecinhas
f8083bfc50 Report fatal errors instead of segfaulting/asserting on a few invalid accesses while reading MachO files.
Summary:
Shift an older “invalid file” test to get a consistent naming for these tests.

Bugs found by afl-fuzz

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6945

llvm-svn: 226219
2015-01-15 22:52:38 +00:00
Lang Hames
9510b7f6fd [Object] Add SF_Exported flag. This flag will be set on all symbols that would
be exported from a dylib if their containing object file were linked into one.

No test case: No command line tools query this flag, and there are no Object
unit tests.

llvm-svn: 226217
2015-01-15 22:33:30 +00:00
Sanjoy Das
618e939258 Revert r226201 (Add a new pass "inductive range check elimination")
The change used C++11 features not supported by MSVC 2012.  I will fix
the change to use things supported MSVC 2012 and recommit shortly.

llvm-svn: 226216
2015-01-15 22:18:10 +00:00
David Majnemer
3affad4957 InductiveRangeCheckElimination: Remove extra ';'
This silences a GCC warning.

llvm-svn: 226215
2015-01-15 21:55:16 +00:00
Andrew Kaylor
c921a5c529 Fixing pedantic build warnings.
llvm-svn: 226214
2015-01-15 21:50:53 +00:00
Colin LeMahieu
d02bf117bc [Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.
llvm-svn: 226210
2015-01-15 21:35:49 +00:00
Hal Finkel
dcf8b14857 [PowerPC] Loosen ELFv1 PPC64 func descriptor loads for indirect calls
Function pointers under PPC64 ELFv1 (which is used on PPC64/Linux on the
POWER7, A2 and earlier cores) are really pointers to a function descriptor, a
structure with three pointers: the actual pointer to the code to which to jump,
the pointer to the TOC needed by the callee, and an environment pointer. We
used to chain these loads, and make them opaque to the rest of the optimizer,
so that they'd always occur directly before the call. This is not necessary,
and in fact, highly suboptimal on embedded cores. Once the function pointer is
known, the loads can be performed ahead of time; in fact, they can be hoisted
out of loops.

Now these function descriptors are almost always generated by the linker, and
thus the contents of the descriptors are invariant. As a result, by default,
we'll mark the associated loads as invariant (allowing them to be hoisted out
of loops). I've added a target feature to turn this off, however, just in case
someone needs that option (constructing an on-stack descriptor, casting it to a
function pointer, and then calling it cannot be well-defined C/C++ code, but I
can imagine some JIT-compilation system doing so).

Consider this simple test:
  $ cat call.c

  typedef void (*fp)();
  void bar(fp x) {
    for (int i = 0; i < 1600000000; ++i)
      x();
  }

  $ cat main.c

  typedef void (*fp)();
  void bar(fp x);
  void foo() {}
  int main() {
    bar(foo);
  }

On the PPC A2 (the BG/Q supercomputer), marking the function-descriptor loads
as invariant brings the execution time down to ~8 seconds from ~32 seconds with
the loads in the loop.

The difference on the POWER7 is smaller. Compiling with:

  gcc -std=c99 -O3 -mcpu=native call.c main.c : ~6 seconds [this is 4.8.2]

  clang -O3 -mcpu=native call.c main.c : ~5.3 seconds

  clang -O3 -mcpu=native call.c main.c -mno-invariant-function-descriptors : ~4 seconds
  (looks like we'd benefit from additional loop unrolling here, as a first
   guess, because this is faster with the extra loads)

The -mno-invariant-function-descriptors will be added to Clang shortly.

llvm-svn: 226207
2015-01-15 21:17:34 +00:00
Colin LeMahieu
ad558c9627 [Hexagon] Updating indexed load-extend patterns and changing test to new expected output.
llvm-svn: 226206
2015-01-15 21:07:52 +00:00
Sanjoy Das
a7eb1a0b3d Add a new pass "inductive range check elimination"
IRCE eliminates range checks of the form

  0 <= A * I + B < Length

by splitting a loop's iteration space into three segments in a way
that the check is completely redundant in the middle segment.  As an
example, IRCE will convert

  len = < known positive >
  for (i = 0; i < n; i++) {
    if (0 <= i && i < len) {
      do_something();
    } else {
      throw_out_of_bounds();
    }
  }

to

  len = < known positive >
  limit = smin(n, len)
  // no first segment
  for (i = 0; i < limit; i++) {
    if (0 <= i && i < len) { // this check is fully redundant
      do_something();
    } else {
      throw_out_of_bounds();
    }
  }
  for (i = limit; i < n; i++) {
    if (0 <= i && i < len) {
      do_something();
    } else {
      throw_out_of_bounds();
    }
  }


IRCE can deal with multiple range checks in the same loop (it takes
the intersection of the ranges that will make each of them redundant
individually).

Currently IRCE does not do any profitability analysis.  That is a
TODO.

Please note that the status of this pass is *experimental*, and it is
not part of any default pass pipeline.  Having said that, I will love
to get feedback and general input from people interested in trying
this out.

Differential Revision: http://reviews.llvm.org/D6693

llvm-svn: 226201
2015-01-15 20:45:46 +00:00
Hal Finkel
d48111840e Revert "r226086 - Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers""
Reapply r226071 with fixes. Two fixes:

 1. We need to manually remove the old and create the new 'deaf defs'
    associated with physical register definitions when we move the definition of
    the physical register from the copy point to the point of the original vreg def.

    This problem was picked up by the machinstr verifier, and could trigger a
    verification failure on test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll, so I've
    turned on the verifier in the tests.

 2. When moving the def point of the phys reg up, we need to make sure that it
    is neither defined nor read in between the two instructions. We don't, however,
    extend the live ranges of phys reg defs to cover uses, so just checking for
    live-range overlap between the pair interval and the phys reg aliases won't
    pick up reads. As a result, we manually iterate over the range and check for
    reads.

    A test soon to be committed to the PowerPC backend will test this change.

Original commit message:

[RegisterCoalescer] Remove copies to reserved registers

This allows the RegisterCoalescer to join "non-flipped" range pairs with a
physical destination register -- which allows the RegisterCoalescer to remove
copies like this:

<vreg> = something (maybe a load, for example)
... (things that don't use PHYSREG)
PHYSREG = COPY <vreg>

(with all of the restrictions normally applied by the RegisterCoalescer: having
compatible register classes, etc. )

Previously, the RegisterCoalescer handled only the opposite case (copying
*from* a physical register). I don't handle the problem fully here, but try to
get the common case where there is only one use of <vreg> (the COPY).

An upcoming commit to the PowerPC backend will make this pattern much more
common on PPC64/ELF systems.

llvm-svn: 226200
2015-01-15 20:32:09 +00:00
Philip Reames
b8aacc1dea Style cleanup of old gc.root lowering code
Use static functions for helpers rather than static member functions.  a) this changes the linking (minor at best), and b) this makes it obvious no object state is involved.

llvm-svn: 226198
2015-01-15 19:49:25 +00:00
Matt Arsenault
1851a2058d R600/SI: Improve fpext / fptrunc test coverage
llvm-svn: 226197
2015-01-15 19:39:42 +00:00
Philip Reames
38c9dcbb7c clang-format GCStrategy.cpp & GCRootLowering.cpp (NFC)
llvm-svn: 226196
2015-01-15 19:39:17 +00:00
Philip Reames
2743d53c9e Split GCStrategy.cpp into two files (NFC)
This preparation for an update to http://reviews.llvm.org/D6811.  GCStrategy.cpp will hopefully be moving into IR/, where as the lowering logic needs to stay in CodeGen/

llvm-svn: 226195
2015-01-15 19:29:42 +00:00
Colin LeMahieu
14474ecfe7 [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
llvm-svn: 226194
2015-01-15 19:28:32 +00:00
Marek Olsak
5cf742495d R600/SI: Unify VOP2 instructions which are VOP3-only on VI
This removes some duplicated classes and definitions.

These instructions are defined:
  _e32 // pseudo
  _e32_si
  _e64 // pseudo
  _e64_si
  _e64_vi

llvm-svn: 226191
2015-01-15 18:43:06 +00:00
Marek Olsak
6dc07f6738 R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
llvm-svn: 226190
2015-01-15 18:43:01 +00:00
Marek Olsak
9dde9a5c29 R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
These are VOP3-only on VI.

The new multiclass doesn't define VOP3 versions of VOP2 instructions.

llvm-svn: 226189
2015-01-15 18:42:55 +00:00
Marek Olsak
e2d9d70da1 R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
v2: modify hasVALU32BitEncoding instead
v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both
      hasVALU32BitEncoding and AMDGPUMCInstLower::lower
    - report an error if a pseudo can't be lowered
llvm-svn: 226188
2015-01-15 18:42:51 +00:00
Marek Olsak
d720b76451 R600/SI: Add common class VOPAnyCommon
llvm-svn: 226187
2015-01-15 18:42:44 +00:00
Marek Olsak
d751f41714 R600/SI: Don't select SI-only VOP3 opcodes on VI
llvm-svn: 226186
2015-01-15 18:42:40 +00:00
Colin LeMahieu
39bcb9a1e4 [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references.
llvm-svn: 226184
2015-01-15 18:16:00 +00:00
Ramkumar Ramachandra
6658c23924 statepoint tests: use statepoint-example gc
Mechanical conversion of statepoint tests to use the example-statepoint
gc.

llvm-svn: 226183
2015-01-15 18:10:44 +00:00
Joerg Sonnenberger
76e84ed36b Support @PLT loads on 32bit x86.
llvm-svn: 226182
2015-01-15 17:59:02 +00:00
Colin LeMahieu
55264a56e6 [Hexagon] Deleting old float comparison instruction and updating references to new ones.
llvm-svn: 226179
2015-01-15 17:28:14 +00:00
Colin LeMahieu
6ce6625967 [Hexagon] Replacing old fadd/fsub instructions and updating references.
llvm-svn: 226176
2015-01-15 16:30:07 +00:00
Timur Iskhodzhanov
7b5eababde Revert Don't create new comdats in CodeGen
It breaks AddressSanitizer on Windows.

llvm-svn: 226173
2015-01-15 16:14:34 +00:00
Daniel Sanders
ebcb17dfb5 [mips] Fix a typo in the compare patterns for MIPS32r6/MIPS64r6.
Summary: The patterns intended for the SETLE node were actually matching the SETLT node.

Reviewers: atanasyan, sstankovic, vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6997

llvm-svn: 226171
2015-01-15 15:41:03 +00:00
Vasileios Kalintiris
b3567820d5 Fix the C-API MCJIT test for 32-bit big endian machines.
Avoid using unions for storing the return value from
LLVMGetGlobalValueAddress() and LLVMGetFunctionAddress() and accessing it as
a pointer through another pointer member. This causes problems on 32-bit big
endian machines since the pointer gets the higher part of the return value of
the aforementioned functions.

llvm-svn: 226170
2015-01-15 15:36:04 +00:00
Vladimir Medic
68db5bdb63 Add disassembler tests for mips64r6 platform. There are no functional changes.
llvm-svn: 226166
2015-01-15 14:18:12 +00:00
Vladimir Medic
d7462ab6c7 Add disassembler tests for mips32r6 platform. There are no functional changes.
llvm-svn: 226165
2015-01-15 14:11:38 +00:00
Vladimir Medic
4f5cb92c60 Add disassembler tests for mips64r2 platform. There are no functional changes.
llvm-svn: 226164
2015-01-15 14:06:34 +00:00
Mehdi Amini
be6225a8f6 Fix SelectionDAG -view-*-dags filtering
llvm-svn: 226163
2015-01-15 12:03:32 +00:00
Alexander Kornienko
66580103e2 Replace size method call of containers to empty method where appropriate
This patch was generated by a clang tidy checker that is being open sourced.
The documentation of that checker is the following:

/// The emptiness of a container should be checked using the empty method
/// instead of the size method. It is not guaranteed that size is a
/// constant-time function, and it is generally more efficient and also shows
/// clearer intent to use empty. Furthermore some containers may implement the
/// empty method but not implement the size method. Using empty whenever
/// possible makes it easier to switch to another container in the future.

Patch by Gábor Horváth!

llvm-svn: 226161
2015-01-15 11:41:30 +00:00
Chandler Carruth
0a49f1bfc1 [PM] Port TargetLibraryInfo to the new pass manager, provided by the
TargetLibraryAnalysis pass.

There are actually no direct tests of this already in the tree. I've
added the most basic test that the pass manager bits themselves work,
and the TLI object produced will be tested by an upcoming patches as
they port passes which rely on TLI.

This is starting to point out the awkwardness of the invalidate API --
it seems poorly fitting on the *result* object. I suspect I will change
it to live on the analysis instead, but that's not for this change, and
I'd rather have a few more passes ported in order to have more
experience with how this plays out.

I believe there is only one more analysis required in order to start
porting instcombine. =]

llvm-svn: 226160
2015-01-15 11:39:46 +00:00
Chandler Carruth
88fd126216 [PM] Separate the TargetLibraryInfo object from the immutable pass.
The pass is really just a means of accessing a cached instance of the
TargetLibraryInfo object, and this way we can re-use that object for the
new pass manager as its result.

Lots of delta, but nothing interesting happening here. This is the
common pattern that is developing to allow analyses to live in both the
old and new pass manager -- a wrapper pass in the old pass manager
emulates the separation intrinsic to the new pass manager between the
result and pass for analyses.

llvm-svn: 226157
2015-01-15 10:41:28 +00:00
Craig Topper
d86e76971b Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.
llvm-svn: 226155
2015-01-15 09:37:15 +00:00
Vladimir Medic
df5781c7e5 Add disassembler tests for mips64 platform. There are no functional changes.
llvm-svn: 226151
2015-01-15 08:50:20 +00:00
David Majnemer
2f29da35a0 SimplifyIndVar: Remove unused variable
OtherOperandIdx is not used anymore, remove it to silence warnings.

llvm-svn: 226138
2015-01-15 07:11:23 +00:00
NAKAMURA Takumi
0068e08baa Update libdeps since TLI was moved from Target to Analysis in r226078.
llvm-svn: 226126
2015-01-15 05:21:00 +00:00
NAKAMURA Takumi
db6ad33f94 Reorder.
llvm-svn: 226125
2015-01-15 05:20:46 +00:00
Hans Wennborg
9aae7d601e utils/release/tag.sh: fix -revision vs. -rc check
llvm-svn: 226124
2015-01-15 04:36:20 +00:00
Chandler Carruth
d706163e8b [PM] Clean up the TLI doxygen comments prior to refactoring this code
for the new pass manager.

llvm-svn: 226089
2015-01-15 03:51:04 +00:00
Hal Finkel
0d21c2bfbe Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Reverting this while I investigate some bad behavior this is causing. As a
possibly-related issue, adding -verify-machineinstrs to one of the test cases
now fails because of this change:

  llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs

*** Bad machine code: No instruction at def index ***
- function:    foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange:   [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0)  0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register:    %DS
Valno #3 is defined at 624r

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange:   [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0)  0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register:    %DS
[624r,624d:3)
LLVM ERROR: Found 2 machine code errors.

where 624r corresponds exactly to the interval combining change:

624B    %RSP<def> = COPY %vreg16; GR64:%vreg16
        Considering merging %vreg16 with %RSP
                RHS = %vreg16 [608r,624r:0)  0@608r
                updated: 608B   %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1]
        Success: %vreg16 -> %RSP
        Result = %RSP

llvm-svn: 226086
2015-01-15 03:08:59 +00:00
Chandler Carruth
9e55180ab4 Switch this header file to not hard-code Windows line endings.
llvm-svn: 226081
2015-01-15 02:21:56 +00:00
Chandler Carruth
49a7633378 [PM] Move TargetLibraryInfo into the Analysis library.
While the term "Target" is in the name, it doesn't really have to do
with the LLVM Target library -- this isn't an abstraction which LLVM
targets generally need to implement or extend. It has much more to do
with modeling the various runtime libraries on different OSes and with
different runtime environments. The "target" in this sense is the more
general sense of a target of cross compilation.

This is in preparation for porting this analysis to the new pass
manager.

No functionality changed, and updates inbound for Clang and Polly.

llvm-svn: 226078
2015-01-15 02:16:27 +00:00
NAKAMURA Takumi
e3f1fa2388 Win64Exception.cpp: Try to fix crash for x64 EH. "Per" might be null there.
llvm-svn: 226077
2015-01-15 02:15:21 +00:00
Sanjoy Das
4b5a4b2975 Fix PR22222
The bug was introduced in r225282. r225282 assumed that sub X, Y is
the same as add X, -Y. This is not correct if we are going to upgrade
the sub to sub nuw. This change fixes the issue by making the
optimization ignore sub instructions.

Differential Revision: http://reviews.llvm.org/D6979

llvm-svn: 226075
2015-01-15 01:46:09 +00:00