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18206 Commits

Author SHA1 Message Date
Evan Cheng
2d09850760 Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng
bde0409264 Add support for hidden visibility to darwin/arm. 
llvm-svn: 35448
 2007-03-29 07:49:34 +00:00
Zhou Sheng
684c2133f2 Clean up some codes in InstCombiner::SimplifyDemandedBits(). 
llvm-svn: 35446
 2007-03-29 04:45:55 +00:00
Evan Cheng
a72a3b7a74 New entries. 
llvm-svn: 35445
 2007-03-29 02:48:56 +00:00
Zhou Sheng
067efd7806 Clean up codes in InstCombiner::SimplifyDemandedBits(): 
1. Line out nested call of APInt::zext/trunc.
2. Make more use of APInt::getHighBitsSet/getLowBitsSet.
3. Use APInt[] operator instead of expression like "APIntVal & SignBit".

llvm-svn: 35444
 2007-03-29 02:26:30 +00:00
Zhou Sheng
74db84591c 1. Make the APInt variable do the binary operation stuff if possible 
instead of using ConstantExpr::getXX.
2. Use constant reference to APInt if possible instead of expensive
   APInt copy.

llvm-svn: 35443
 2007-03-29 01:57:21 +00:00
Jeff Cohen
9193778f39 Fix C Backend to generate code that works with Microsoft C for the benefit of 
front ends that do not depend on the GCC runtime (someday...).

llvm-svn: 35441
 2007-03-28 23:08:37 +00:00
Bill Wendling
0549ae5cdb Made this into a bug report: PR1286 
llvm-svn: 35439
 2007-03-28 19:07:34 +00:00
Anton Korobeynikov
1a8740c88b Oops :) 
llvm-svn: 35438
 2007-03-28 18:38:33 +00:00
Anton Korobeynikov
d59c4e54c7 Don't allow MatchAddress recurse too much. This trims exponential 
behaviour in some cases.

llvm-svn: 35437
 2007-03-28 18:36:33 +00:00
Chris Lattner
a710f7442c add a note 
llvm-svn: 35435
 2007-03-28 18:17:19 +00:00
Chris Lattner
26a37bfd6a Compile CodeGen/X86/lea-3.ll:test2 to: 
_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret

llvm-svn: 35434
 2007-03-28 18:12:31 +00:00
Zhou Sheng
a098617383 Avoid unnecessary APInt construction. 
llvm-svn: 35431
 2007-03-28 17:38:21 +00:00
Chris Lattner
1f18012438 Dan pointed out that this is done, remove it! 
llvm-svn: 35430
 2007-03-28 17:26:52 +00:00
Scott Michel
ae7090641f First test check-in. 
llvm-svn: 35429
 2007-03-28 17:04:43 +00:00
Zhou Sheng
8fecc8c3a0 1. Make more use of getLowBitsSet/getHighBitsSet. 
2. Use APInt[] instead of "X & SignBit".
3. Clean up some codes.
4. Make the expression like "ShiftAmt = ShiftAmtC->getZExtValue()" safe.

llvm-svn: 35424
 2007-03-28 15:02:20 +00:00
Devang Patel
7cde72cbc1 It is not possible to determine dominance between two PHI nodes 
based on their ordering. This is applicable to ETForest::dominates() also.

llvm-svn: 35423
 2007-03-28 14:57:43 +00:00
Zhou Sheng
cf7d99a731 1. Make more use of getLowBitsSet/getHighBitsSet. 
2. Make the APInt value do the zext/trunc stuff instead of using
   ConstantExpr::getZExt().

llvm-svn: 35422
 2007-03-28 09:19:01 +00:00
Evan Cheng
29fcdd1b2f Notes on re-materialization. 
llvm-svn: 35420
 2007-03-28 08:30:04 +00:00
Evan Cheng
13037fbfb4 Move rematerialization out of beta. 
llvm-svn: 35419
 2007-03-28 08:26:40 +00:00
Zhou Sheng
2dc7cf0114 Use UnknownBIts[BitWidth-1] instead of UnknownBIts & SignBits. 
llvm-svn: 35418
 2007-03-28 05:15:57 +00:00
Zhou Sheng
e43a68551e Remove unused APInt variable. 
llvm-svn: 35414
 2007-03-28 03:02:21 +00:00
Reid Spencer
c50c59b4f6 Regenerate. 
llvm-svn: 35411
 2007-03-28 02:37:40 +00:00
Reid Spencer
f88fd1096c Replace the "implementation" keyword with "checkpoint". This more accurately 
describes its function as check against unresolved types and definitions.
This is handy for forcing error messages in assembly test cases or otherwise
ensuring that everything is resolved at that point in the assembly.

llvm-svn: 35410
 2007-03-28 02:36:42 +00:00
Zhou Sheng
7245616070 Clean up codes in ComputeMaskedBits(): 
1. Line out nested use of zext/trunc.
2. Make more use of getHighBitsSet/getLowBitsSet.
3. Use APInt[] != 0 instead of "(APInt & SignBit) != 0".

llvm-svn: 35408
 2007-03-28 02:19:03 +00:00
Evan Cheng
13cc34e91b Scale 1 is always ok. 
llvm-svn: 35407
 2007-03-28 01:55:52 +00:00
Evan Cheng
a55449c051 Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Reid Spencer
bd89a6ea1c No need to generate the implementation keyword any more. Its frivolous. 
llvm-svn: 35405
 2007-03-28 01:53:20 +00:00
Evan Cheng
6056fd729d GEP index sinking fixes: 
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
 2007-03-28 01:49:39 +00:00
Reid Spencer
3b614f9dad For PR1280: 
When converting an add/xor/and triplet into a trunc/sext, only do so if the
intermediate integer type is a bitwidth that the targets can handle.

llvm-svn: 35400
 2007-03-28 01:36:16 +00:00
Evan Cheng
a182608846 Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should 
not violate that.

llvm-svn: 35396
 2007-03-28 01:30:37 +00:00
Bill Wendling
e8eccb1684 Remove cruft I put in there... 
llvm-svn: 35394
 2007-03-28 01:02:54 +00:00
Chris Lattner
9f59529c61 Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the 
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393
 2007-03-28 00:58:40 +00:00
Bill Wendling
1087888176 Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. 
llvm-svn: 35392
 2007-03-28 00:57:11 +00:00
Bill Wendling
6b555c80c0 Add the "unpack low packed data" instructions. This should be the last of 
the MMX instructions that are needed...

llvm-svn: 35389
 2007-03-27 21:20:36 +00:00
Devang Patel
67eede36f7 Use SmallPtrSet. 
llvm-svn: 35388
 2007-03-27 20:50:46 +00:00
Bill Wendling
d43819da2f Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.

llvm-svn: 35385
 2007-03-27 20:22:40 +00:00
Evan Cheng
a23cc41b11 Unbreaks non-debug builds. 
llvm-svn: 35383
 2007-03-27 16:44:48 +00:00
Lauro Ramos Venancio
99fca527d3 "The C standards do say that "char" may either be a "signed char" or "unsigned 
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php

llvm-svn: 35382
 2007-03-27 16:33:08 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Anton Korobeynikov
64622a0ddf Remove dead code 
llvm-svn: 35380
 2007-03-27 12:05:48 +00:00
Anton Korobeynikov
b58a93156f Split big monster into small helpers. No functionality change. 
llvm-svn: 35379
 2007-03-27 11:29:11 +00:00
Evan Cheng
7218d782fe SDISel does not preserve all, it changes CFG and other info. 
llvm-svn: 35376
 2007-03-27 00:53:36 +00:00
Evan Cheng
c81bdb4100 Don't call getOperandConstraint() if operand index is greater than 
TID->numOperands.

llvm-svn: 35375
 2007-03-27 00:48:28 +00:00
Devang Patel
8330ee3120 Spell check. 
llvm-svn: 35374
 2007-03-27 00:16:08 +00:00
Reid Spencer
e4b331a4f2 Implement some minor review feedback. 
llvm-svn: 35373
 2007-03-26 23:58:26 +00:00
Reid Spencer
0cdfe48fc8 For PR1271: 
Fix another incorrectly converted shift mask.

llvm-svn: 35371
 2007-03-26 23:45:51 +00:00
Devang Patel
c2708c8ccb Reduce malloc/free traffic. 
llvm-svn: 35370
 2007-03-26 23:19:29 +00:00
Devang Patel
58a8e74de6 It is not possible to determie dominance between two PHI nodes 
based on their ordering.

llvm-svn: 35369
 2007-03-26 23:18:28 +00:00
Devang Patel
3062ae001d Use std::vector<DFCalculateWorkObject> instead of 
std::vector<DFCalculateWorkObject *> to reduce malloc/free traffic.

llvm-svn: 35368
 2007-03-26 23:17:19 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Evan Cheng
0ff19780f9 Fix for PR1266. Don't mark a two address operand IsKill. 
llvm-svn: 35365
 2007-03-26 22:40:42 +00:00
Evan Cheng
201771637e Change findRegisterUseOperand() to return operand index instead. 
llvm-svn: 35363
 2007-03-26 22:37:45 +00:00
Dale Johannesen
3ad8ab7b61 Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 
hopefully forestall similar errors.

llvm-svn: 35362
 2007-03-26 22:23:54 +00:00
Chris Lattner
16700ef424 eliminate use of std::set 
llvm-svn: 35361
 2007-03-26 20:40:50 +00:00
Reid Spencer
4af99334ea Add a comment to explain a folding transform. 
llvm-svn: 35360
 2007-03-26 20:09:02 +00:00
Reid Spencer
73d778edb7 Get better debug output by having modified instructions print both the 
original and new instruction. A slight performance hit with ostringstream
but it is only for debug.
Also, clean up an uninitialized variable warning noticed in a release build.

llvm-svn: 35358
 2007-03-26 17:44:01 +00:00
Reid Spencer
3fea170ecd Get the number of bits to set in a mask correct for a shl/lshr transform. 
llvm-svn: 35357
 2007-03-26 17:18:58 +00:00
Bill Wendling
8065cc3173 Promote to v1i64 type... 
llvm-svn: 35353
 2007-03-26 08:03:33 +00:00
Bill Wendling
3c4e130b77 Updated. 
llvm-svn: 35352
 2007-03-26 07:55:58 +00:00
Bill Wendling
a42484728c Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Evan Cheng
5b1c21d27b SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Reid Spencer
a6a4dbd24e For PR1271: 
Fix SingleSource/Regression/C/2003-05-21-UnionBitFields.c by changing a
getHighBitsSet call to getLowBitsSet call that was incorrectly converted
from the original lshr constant expression.

llvm-svn: 35348
 2007-03-26 05:25:00 +00:00
Dale Johannesen
43fc14d6e4 Look through bitcast when finding IVs. (Chris' patch really.) 
llvm-svn: 35347
 2007-03-26 03:01:27 +00:00
Reid Spencer
4d3d7d0f2a For PR1271: 
Remove a use of getLowBitsSet that caused the mask used for replacement of
shl/lshr pairs with an AND instruction to be computed incorrectly. Its not
clear exactly why this is the case. This solves the disappearing shifts
problem, but it doesn't fix Regression/C/2003-05-21-UnionBitFields. It
seems there is more going on.

llvm-svn: 35342
 2007-03-25 21:11:44 +00:00
Chris Lattner
26cfd91db8 implement Transforms/InstCombine/cast2.ll:test3 and PR1263 
llvm-svn: 35341
 2007-03-25 20:43:09 +00:00
Reid Spencer
1677543a3a Some cleanup from review: 
* Don't assume shift amounts are <= 64 bits
* Avoid creating an extra APInt in SubOne and AddOne by using -- and ++
* Add another use of getLowBitsSet
* Convert a series of if statements to a switch

llvm-svn: 35339
 2007-03-25 19:55:33 +00:00
Anton Korobeynikov
6f78c59650 First step of switch lowering refactoring: perform worklist-driven 
strategy, emit JT's where possible.

llvm-svn: 35338
 2007-03-25 15:07:15 +00:00
Anton Korobeynikov
a5e854461f Fix authorship 
llvm-svn: 35337
 2007-03-25 13:44:26 +00:00
Chris Lattner
f4ff1dc689 fold constantexprs more aggressively, fixing PR1265 
llvm-svn: 35336
 2007-03-25 05:47:04 +00:00
Reid Spencer
8449e5fa0e Refactor several ConstantExpr::getXXX calls with ConstantInt arguments 
using the facilities of APInt. While this duplicates a tiny fraction of
the constant folding code, it also makes the code easier to read and
avoids large ConstantExpr overhead for simple, known computations.

llvm-svn: 35335
 2007-03-25 05:33:51 +00:00
Chris Lattner
ee90a087a6 add a note 
llvm-svn: 35334
 2007-03-25 05:10:46 +00:00
Zhou Sheng
3312a86598 1. Avoid unnecessary APInt construction if possible. 
2. Use isStrictlyPositive() instead of isPositive() in two places where
   they need APInt value > 0 not only >=0.

llvm-svn: 35333
 2007-03-25 05:01:29 +00:00
Chris Lattner
6f17a615cb Implement support for vector operands to inline asm, implementing 
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
 2007-03-25 05:00:54 +00:00
Chris Lattner
6d8bbccee0 add a note 
llvm-svn: 35330
 2007-03-25 04:46:28 +00:00
Chris Lattner
31c6763051 Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll 
llvm-svn: 35329
 2007-03-25 04:44:03 +00:00
Chris Lattner
4a7feb72f5 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
llvm-svn: 35327
 2007-03-25 04:35:41 +00:00
Reid Spencer
e601991a5e Make more uses of getHighBitsSet and get rid of some pointless & of an 
APInt with its type mask.

llvm-svn: 35325
 2007-03-25 04:26:16 +00:00
Chris Lattner
91adfbe0ff Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
llvm-svn: 35324
 2007-03-25 02:18:14 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Reid Spencer
676eeb9c94 More APIntification: 
* Convert the last use of a uint64_t that should have been an APInt.
* Change ComputeMaskedBits to have a const reference argument for the Mask
  so that recursions don't cause unneeded temporaries. This causes temps
  to be needed in other places (where the mask has to change) but this
  change optimizes for the recursion which is more frequent.
* Remove two instances of &ing a Mask with getAllOnesValue. Its not
  needed any more because APInt is accurate in its bit computations.
* Start using the getLowBitsSet and getHighBits set methods on APInt
  instead of shifting. This makes it more clear in the code what is
  going on.

llvm-svn: 35321
 2007-03-25 02:03:12 +00:00
Chris Lattner
18c3c6a01d Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner
104e73382c enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner
92e2ee7b2d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Chris Lattner
3f71a6b498 fix a regression on vector or instructions. 
llvm-svn: 35314
 2007-03-24 23:56:43 +00:00
Chris Lattner
57d0c197e6 don't rely on ADL 
llvm-svn: 35299
 2007-03-24 17:37:03 +00:00
Chris Lattner
3a16450eaf add a valuetype for v1i64, which is needed by mmx. 
llvm-svn: 35298
 2007-03-24 17:36:26 +00:00
Zhou Sheng
ce8c7becec Make some codes more efficient. 
llvm-svn: 35297
 2007-03-24 15:34:37 +00:00
Chris Lattner
a04981fbda add a bad case evan though of. 
llvm-svn: 35296
 2007-03-24 06:01:32 +00:00
Reid Spencer
b03fc33244 For PR1205: 
Convert some calls to ConstantInt::getZExtValue() into getValue() and
use APInt facilities in the subsequent computations.

llvm-svn: 35294
 2007-03-24 00:42:08 +00:00
Evan Cheng
a484f31d4b Adjust offset to compensate for big endian machines. 
llvm-svn: 35293
 2007-03-24 00:02:43 +00:00
Anton Korobeynikov
63bff8af0c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling
124f2c8706 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Evan Cheng
84aecc56e7 Make sure SEXTLOAD of the specific type is supported on the target. 
llvm-svn: 35289
 2007-03-23 22:13:36 +00:00
Reid Spencer
01d252add1 For PR1205: 
* APIntify visitAdd and visitSelectInst
* Remove unused uint64_t versions of utility functions that have been
  replaced with APInt versions.
This completes most of the changes for APIntification of InstCombine. This
passes llvm-test and llvm/test/Transforms/InstCombine/APInt.

Patch by Zhou Sheng.

llvm-svn: 35287
 2007-03-23 21:24:59 +00:00
Evan Cheng
7dd7666120 Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
llvm-svn: 35286
 2007-03-23 20:55:21 +00:00
Reid Spencer
da8ec61ec4 For PR1205: 
APIntify visitDiv, visitMul and visitRem.

Patch by Zhou Sheng.

llvm-svn: 35283
 2007-03-23 20:05:17 +00:00
Chris Lattner
04baffb0c5 switch AddReachableCodeToWorklist from being recursive to being iterative. 
llvm-svn: 35282
 2007-03-23 19:17:18 +00:00
Reid Spencer
1fd12cf9f6 For PR1205: 
APIntify several utility functions supporting logical operators and shift
operators.

Patch by Zhou Sheng.

llvm-svn: 35281
 2007-03-23 18:46:34 +00:00
Reid Spencer
7a9c981d80 Fix constant fold of div by zero and rem by zero to match IEEE 754 
requirements. We must return NaN in some cases and correctly signed
infinity in other cases. Passes CFP2006 (not that that says much).

llvm-svn: 35277
 2007-03-23 05:33:23 +00:00
Zhou Sheng
e706d8f56d Make the "KnownZero ^ TypeMask" computation just once. 
llvm-svn: 35276
 2007-03-23 03:13:21 +00:00
Zhou Sheng
6b7b4945f1 Simplify the code. 
llvm-svn: 35275
 2007-03-23 02:39:25 +00:00
Evan Cheng
62ccdaea67 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
 2007-03-23 02:16:52 +00:00
Reid Spencer
9881580cec For PR1205: 
APInt support for logical operators in visitAnd, visitOr, and visitXor.

Patch by Zhou Sheng.

llvm-svn: 35273
 2007-03-22 22:19:58 +00:00
Reid Spencer
74288268d3 For PR1205: 
* APIntify commonIntCastTransforms
* APIntify visitTrunc
* APIntify visitZExt

Patch by Zhou Sheng.

llvm-svn: 35271
 2007-03-22 20:56:53 +00:00
Reid Spencer
b6c09a009e For PR1205: 
* Re-enable the APInt version of MaskedValueIsZero.
* APIntify the Comput{Un}SignedMinMaxValuesFromKnownBits functions
* APIntify visitICmpInst.

llvm-svn: 35270
 2007-03-22 20:36:03 +00:00
Bill Wendling
e6a9c6dfe6 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling
1bcad4c1cd Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dan Gohman
d0a0ea9916 Change uses of Function::front to Function::getEntryBlock for readability. 
llvm-svn: 35265
 2007-03-22 16:38:57 +00:00
Reid Spencer
a2d8b5e7a1 Add the NoUnwind function attribute. 
llvm-svn: 35260
 2007-03-22 02:14:48 +00:00
Reid Spencer
620297a20c Regenerate. 
llvm-svn: 35259
 2007-03-22 02:14:08 +00:00
Reid Spencer
6890147648 Add support for the noreturn and nounwind function attributes. 
llvm-svn: 35258
 2007-03-22 02:13:23 +00:00
Nick Lewycky
428523f51a Fix broken optimization disabled by a logic bug. 
Analyze GEPs. If the indices are all zero, transfer whether the pointer is
known to be not null through the GEP.

Add a few more cases for xor and shift instructions.

llvm-svn: 35257
 2007-03-22 02:02:51 +00:00
Evan Cheng
d7be4893f4 More opportunities to reduce load size. 
llvm-svn: 35254
 2007-03-22 01:54:19 +00:00
Evan Cheng
da92165bab Fix for PR1257. Bug in live range shortening as a result of copy coalescing 
where the destination is dead.

llvm-svn: 35252
 2007-03-22 01:26:05 +00:00
Reid Spencer
bdfbda05fb For PR1248: 
* Fix some indentation and comments in InsertRangeTest
* Add an "IsSigned" parameter to AddWithOverflow and make it handle signed
  additions. Also, APIntify this function so it works with any bitwidth.
* For the icmp pred ([us]div %X, C1), C2 transforms, exit early if the
  div instruction's RHS is zero.
* Finally, for icmp pred (sdiv %X, C1), -C2, fix an off-by-one error. The
  HiBound needs to be incremented in order to get the range test correct.

llvm-svn: 35247
 2007-03-21 23:19:50 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Anton Korobeynikov
c0842af02d Add TODO list for MSIL backend 
llvm-svn: 35244
 2007-03-21 21:48:59 +00:00
Anton Korobeynikov
bc43d296b2 Let the new backend begin! 
llvm-svn: 35242
 2007-03-21 21:38:25 +00:00
Dale Johannesen
fb7b59f5dd add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Evan Cheng
9867632e64 fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
llvm-svn: 35239
 2007-03-21 20:14:05 +00:00
Nicolas Geoffray
205541ef78 Protect R31's frame offset from being used by callee-saved registers, when R31 
is the frame pointer.

llvm-svn: 35233
 2007-03-21 16:44:14 +00:00
Zhou Sheng
427b6bec97 Fix a bug in getAllOnesValue() which broke 
some test cases for bitwidth > 64.

llvm-svn: 35232
 2007-03-21 04:34:37 +00:00
Evan Cheng
00a5cbf9e7 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng
fb9c4c2edc Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Evan Cheng
516a83595d Potential spiller improvement. 
llvm-svn: 35228
 2007-03-20 22:22:38 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Dale Johannesen
50a22f6fe6 maintain LiveIn when splitting blocks (register scavenging needs it) 
llvm-svn: 35226
 2007-03-20 21:35:06 +00:00
Devang Patel
3a426e1c86 DominanceFrontier::calculate(). 
Avoid recursion, Use iterative algorithm.

llvm-svn: 35225
 2007-03-20 21:25:31 +00:00
Jeff Cohen
8dea6ada6f Fix some VC++ warnings. 
llvm-svn: 35224
 2007-03-20 20:43:18 +00:00
Jeff Cohen
21c7fc9c1f Fix (and simplify) 48-bit byte swap. 
Get pos/neg infinity the correct way.

llvm-svn: 35223
 2007-03-20 20:42:36 +00:00
Devang Patel
18146cf2a2 LoopSimplify::FindPHIToPartitionLoops() 
Use ETForest instead of DominatorSet.

llvm-svn: 35221
 2007-03-20 20:18:12 +00:00
Lauro Ramos Venancio
632ac0e289 Code clean up. 
llvm-svn: 35220
 2007-03-20 20:09:03 +00:00
Evan Cheng
fe301e0f29 Minor bug. 
llvm-svn: 35219
 2007-03-20 19:32:11 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Reid Spencer
d37f0f007d Regenerate. 
llvm-svn: 35215
 2007-03-20 17:19:31 +00:00
Reid Spencer
3cc307f4d7 Don't delete things before their last use (avoids bad reads). 
llvm-svn: 35214
 2007-03-20 17:18:33 +00:00
Lauro Ramos Venancio
9659c8befc CopyToReg source operand can be a physical register. 
llvm-svn: 35213
 2007-03-20 16:46:44 +00:00
Zhou Sheng
0ae1c9e1ad Simplify isHighOnes(). 
llvm-svn: 35211
 2007-03-20 12:49:06 +00:00
Evan Cheng
0176b9859d First cut trivial re-materialization support. 
llvm-svn: 35208
 2007-03-20 08:13:50 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
11976abd1e New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
b9cc0ade43 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner
1ed603c0d9 fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Reid Spencer
81602be7e3 Regenerate. 
llvm-svn: 35199
 2007-03-20 01:13:36 +00:00
Reid Spencer
4a8b426ab2 Plug some PATypeHolder memory leaks. 
llvm-svn: 35198
 2007-03-20 01:13:00 +00:00
Dale Johannesen
516d98c710 use types of loads and stores, not address, in CheckForIVReuse 
llvm-svn: 35197
 2007-03-20 00:47:50 +00:00
Dale Johannesen
c526b970ce fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Chris Lattner
6dbed4d4ca Fix a nasty memory leak, caused by my revamp of the value symbol table. 
llvm-svn: 35195
 2007-03-20 00:18:10 +00:00
Reid Spencer
2f1ee85f90 Make isOneBitSet faster by using APInt::isPowerOf2. Thanks Chris. 
llvm-svn: 35194
 2007-03-20 00:16:52 +00:00
Reid Spencer
a792b71ab3 APIntify the isHighOnes utility function. 
llvm-svn: 35190
 2007-03-19 21:29:50 +00:00
Reid Spencer
41d254c7f4 Fix coding standards violation. 
llvm-svn: 35189
 2007-03-19 21:19:02 +00:00
Reid Spencer
4009f1eacb Implement isMaxValueMinusOne in terms of APInt instead of uint64_t. 
Patch by Sheng Zhou.

llvm-svn: 35188
 2007-03-19 21:10:28 +00:00
Reid Spencer
57a15f4445 Implement isMinValuePlusOne using facilities of APInt instead of uint64_t 
Patch by Zhou Sheng.

llvm-svn: 35187
 2007-03-19 21:08:07 +00:00
Reid Spencer
1985e3645b Implement isOneBitSet in terms of APInt::countPopulation. 
llvm-svn: 35186
 2007-03-19 21:04:43 +00:00
Reid Spencer
367a2917c0 1. Use APInt::getSignBit to reduce clutter (patch by Sheng Zhou) 
2. Replace uses of the "isPositive" utility function with APInt::isPositive

llvm-svn: 35185
 2007-03-19 20:58:18 +00:00
Reid Spencer
49ea42b719 Remove a redundant clause in an if statement. 
Patch by Sheng Zhou.

llvm-svn: 35184
 2007-03-19 20:47:50 +00:00
Reid Spencer
ea5bcde3c8 Regenerate. 
llvm-svn: 35183
 2007-03-19 20:40:51 +00:00
Reid Spencer
7f92fc05cd Fix test/Assembler/2007-03-19-NegValue.ll by using the new "isSigned" 
parameter on ConstantInt::get to indicate the signedness of the intended
value.

llvm-svn: 35182
 2007-03-19 20:40:22 +00:00
Reid Spencer
7d20e42a97 Allow ConstantInt::get(Ty, uint64_t) to interpret the 64-bit values as a 
negative number. This is needed to fix test/Assembler/2007-03-19-NegValue.ll

llvm-svn: 35181
 2007-03-19 20:39:08 +00:00
Reid Spencer
b7d0a60da1 Implement extension of sign bits for negative values in the uint64_t 
constructor. This helps to fix test/Assembler/2007-03-19-NegValue.ll

llvm-svn: 35180
 2007-03-19 20:37:47 +00:00
Anton Korobeynikov
62e2448864 Fix mingw32 build 
llvm-svn: 35177
 2007-03-19 20:19:08 +00:00
Reid Spencer
65e272dedd Regenerate. 
llvm-svn: 35174
 2007-03-19 18:40:50 +00:00
Reid Spencer
a304595278 For PR1248: 
Eliminate support for type planes in numbered values. This simplifies the
data structures involved in managing forward definitions, etc. Instead of
requiring maps from type to value, we can now just use a vector of values.
These changes also required rewrites of some support functions such as
InsertValue, getBBVal, and ResolveDefinitions. Some other cosmetic changes
were made as well.

llvm-svn: 35173
 2007-03-19 18:39:36 +00:00
Reid Spencer
34f69893be Add and Operator== method to ValID so equality can be done properly for 
named or numbered ValIDs.

llvm-svn: 35172
 2007-03-19 18:34:28 +00:00
Reid Spencer
135ca5e8c4 For PR1258: 
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.

llvm-svn: 35171
 2007-03-19 18:32:53 +00:00
Chris Lattner
5f1d3ac7e4 fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll 
llvm-svn: 35169
 2007-03-19 18:25:57 +00:00
Evan Cheng
822f7b5213 Remove -reduce-joining-phys-regs options. Make it on by default. 
llvm-svn: 35165
 2007-03-19 18:08:26 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng
498f19548c Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Evan Cheng
3b690ab936 Minor bug fix. 
llvm-svn: 35153
 2007-03-19 04:22:35 +00:00
Chris Lattner
59fe2be1c4 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner
5e2e3ddb7e implement the next chunk of SROA with memset/memcpy's of aggregates. This 
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

llvm-svn: 35150
 2007-03-19 00:16:43 +00:00
Nick Lewycky
2a51ea0c0e Clean up this code and fix subtract miscompile. 
llvm-svn: 35146
 2007-03-18 22:58:46 +00:00
Chris Lattner
adf7003452 Implement InstCombine/and-xor-merge.ll:test[12]. 
Rearrange some code to simplify it now that shifts are binops

llvm-svn: 35145
 2007-03-18 22:51:34 +00:00
Chris Lattner
a1df6908d2 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky
04ecc07c25 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Evan Cheng
b4713633aa - Merge UsedBlocks info after two virtual registers are coalesced. 
- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141
 2007-03-18 09:05:55 +00:00
Evan Cheng
76df6abc61 Keep UsedBlocks info accurate. 
llvm-svn: 35140
 2007-03-18 09:02:31 +00:00
Nick Lewycky
41f13d431a Propagate ValueRanges across equality. 
Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138
 2007-03-18 01:09:32 +00:00
Anton Korobeynikov
b34e09291b Silence warning 
llvm-svn: 35137
 2007-03-17 14:48:06 +00:00
Evan Cheng
5be8544e8a Track the BB's where each virtual register is used. 
llvm-svn: 35135
 2007-03-17 09:29:54 +00:00
Evan Cheng
ca1e6eea8e Joining a live interval of a physical register with a virtual one can turn out 
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134
 2007-03-17 09:27:35 +00:00
Evan Cheng
65d69fe08d Use SmallSet instead of std::set. 
llvm-svn: 35133
 2007-03-17 08:53:30 +00:00
Evan Cheng
8552300ab1 If sdisel has decided to sink GEP index expression into any BB. Replace all uses 
in that BB.

llvm-svn: 35132
 2007-03-17 08:22:49 +00:00
Devang Patel
2dabb16eac Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng
77099bef05 Turn on GEP index sinking by default. 
llvm-svn: 35127
 2007-03-16 18:32:30 +00:00
Evan Cheng
449900b988 Stupid bug. 
llvm-svn: 35126
 2007-03-16 17:50:20 +00:00
Bill Wendling
8ced23ee5a And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng
c3e7d4b884 Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
 2007-03-16 08:46:27 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng
ce8b779c6c Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.

llvm-svn: 35121
 2007-03-16 08:42:32 +00:00
Nick Lewycky
de44438e24 Add more comments and update to new asm syntax. 
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119
 2007-03-16 02:37:39 +00:00
Bill Wendling
feaff80149 Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng
ab9145d617 Debugging output stuff. 
llvm-svn: 35117
 2007-03-15 21:19:28 +00:00
Evan Cheng
dc6ba035bc Estimate a cost using the possible number of scratch registers required and use 
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
 2007-03-14 22:43:40 +00:00
Evan Cheng
00edaa08b5 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712 Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Evan Cheng
371b8e8fa9 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Zhou Sheng
5c6399dab7 ShiftAmt might equal to zero. Handle this situation. 
llvm-svn: 35094
 2007-03-14 09:07:33 +00:00
Zhou Sheng
4415c2647e Enable KnownZero/One.clear(). 
llvm-svn: 35093
 2007-03-14 03:21:24 +00:00
Evan Cheng
399f56eac2 Try schedule def + use closer whne Sethi-Ullman numbers are the same. 
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
 2007-03-13 23:25:11 +00:00
Evan Cheng
7cbde8351a AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Evan Cheng
bd964bd8eb Correct type info for isLegalAddressImmediate() check. 
llvm-svn: 35086
 2007-03-13 20:34:37 +00:00
Nicolas Geoffray
9c77df75ea Stack and register alignment of call arguments in the ELF ABI 
llvm-svn: 35083
 2007-03-13 15:02:46 +00:00
Chris Lattner
efc2339bd7 ifdef out some dead code. 
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082
 2007-03-13 14:27:42 +00:00
Zhou Sheng
7cf2811ab3 For expression like 
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080
 2007-03-13 06:40:59 +00:00
Zhou Sheng
14cef9ec74 In APInt version ComputeMaskedBits(): 
1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078
 2007-03-13 02:23:10 +00:00
Evan Cheng
92712d4884 Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng
b2a5499d86 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35076
 2007-03-12 23:37:10 +00:00
Evan Cheng
7767159f08 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng
06d83c8fce More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35074
 2007-03-12 23:29:01 +00:00
Evan Cheng
0eeb8b59eb More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.

llvm-svn: 35073
 2007-03-12 23:28:50 +00:00
Evan Cheng
1fcdd7e1e5 Use new TargetLowering addressing modes hooks. 
llvm-svn: 35072
 2007-03-12 23:27:37 +00:00
Evan Cheng
4224fa3617 Stupid bug: SSE2 supports v2i64 add / sub. 
llvm-svn: 35070
 2007-03-12 22:58:52 +00:00
Reid Spencer
7be576b4b0 Revert the last patch as it violates the conditions of sext/zext. 
llvm-svn: 35068
 2007-03-12 18:37:25 +00:00
Jeff Cohen
4e667fd766 Unbreak C++ build. 
llvm-svn: 35067
 2007-03-12 17:57:00 +00:00
Jeff Cohen
91930bc4d4 Unbreak VC++ build. Do not use identifiers starting with _ as they are reserved and 
can collide with system defined names.  Windows defines _BB, for example.

llvm-svn: 35066
 2007-03-12 17:56:27 +00:00
Zhou Sheng
0145067d85 For APInt::z/sext(width), if width == BitWidth, just return *this. 
llvm-svn: 35065
 2007-03-12 17:47:45 +00:00
Reid Spencer
d59425085f Add an APInt version of SimplifyDemandedBits. 
Patch by Zhou Sheng.

llvm-svn: 35064
 2007-03-12 17:25:59 +00:00
Reid Spencer
b18f916bbe Add an APInt version of ShrinkDemandedConstant. 
Patch by Zhou Sheng.

llvm-svn: 35063
 2007-03-12 17:15:10 +00:00
Zhou Sheng
c8583ff888 Avoid to assert on "(KnownZero & KnownOne) == 0". 
llvm-svn: 35062
 2007-03-12 16:54:56 +00:00
Zhou Sheng
c9c53385b8 In function ComputeMaskedBits(): 
1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

llvm-svn: 35060
 2007-03-12 05:44:52 +00:00
Nick Lewycky
8a08bcfbe7 Add value ranges. Currently inefficient in both execution time and 
optimization power.

llvm-svn: 35058
 2007-03-10 18:12:48 +00:00
Anton Korobeynikov
0c2d312725 Use range tests in LowerSwitch, where possible 
llvm-svn: 35057
 2007-03-10 16:46:28 +00:00
Nick Lewycky
2af4a3ab17 Add getter methods for the extremes of a ConstantRange. 
llvm-svn: 35056
 2007-03-10 15:54:12 +00:00
Bill Wendling
236cfc4344 Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.

llvm-svn: 35055
 2007-03-10 09:57:05 +00:00
Devang Patel
20b8163ad3 Remove dead comments. 
llvm-svn: 35053
 2007-03-09 23:41:03 +00:00
Devang Patel
8a26f4caa0 Avoid recursion. Use iterative algorithm for RenamePass(). 
llvm-svn: 35052
 2007-03-09 23:39:14 +00:00
Devang Patel
ca60446cb4 Increment iterator now because IVUseShouldUsePostIncValue may remove 
User from the list of I users.

llvm-svn: 35051
 2007-03-09 21:19:53 +00:00
Reid Spencer
75ffe11ca9 Regenerate. 
llvm-svn: 35050
 2007-03-09 21:19:09 +00:00
Evan Cheng
a4e410aa9c Minor stuff. 
llvm-svn: 35049
 2007-03-09 19:46:06 +00:00
Evan Cheng
d7201d12af Add comments about LSR / ARM. 
llvm-svn: 35048
 2007-03-09 19:35:33 +00:00
Evan Cheng
2e6f19d8c8 Unfinished work and ideas related to register scavenger. 
llvm-svn: 35047
 2007-03-09 19:34:51 +00:00
Reid Spencer
f860fd3370 For PR1245: 
Account for the sign bit when computing the number of bits required for
a negative integer literal constant.

llvm-svn: 35046
 2007-03-09 19:26:52 +00:00
Dale Johannesen
10a05b538d apply comments from review of last patch 
llvm-svn: 35045
 2007-03-09 19:18:59 +00:00
Dale Johannesen
23c2498e23 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.

llvm-svn: 35044
 2007-03-09 17:58:17 +00:00
Anton Korobeynikov
f8f0ce564c Unbreak mingw32 build 
llvm-svn: 35042
 2007-03-09 11:53:34 +00:00
Evan Cheng
dc9f790abd If a virtual register is already marked alive in this block, that means it is 
alive in one of the successor block. Do not add it to the kill list.

llvm-svn: 35041
 2007-03-09 09:48:56 +00:00
Evan Cheng
e7ba7ee5d8 Print preds / succs BB numbers. 
llvm-svn: 35040
 2007-03-09 08:29:08 +00:00
Evan Cheng
0049744cd8 Avoid variable shadowing. 
llvm-svn: 35039
 2007-03-09 06:02:17 +00:00