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224 Commits

Author SHA1 Message Date
Akira Hatanaka
d01b04ad93 [mips] Refactor instructions which move data from or to coprocessors. 
llvm-svn: 171510
 2013-01-04 19:13:49 +00:00
Akira Hatanaka
6d30f89eeb [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.

llvm-svn: 170956
 2012-12-21 23:21:32 +00:00
Akira Hatanaka
b41ed048b6 [mips] Refactor SYNC and multiply/divide instructions. 
llvm-svn: 170955
 2012-12-21 23:17:36 +00:00
Akira Hatanaka
6b9b8a5489 [mips] Refactor BAL instructions. 
llvm-svn: 170954
 2012-12-21 23:15:59 +00:00
Akira Hatanaka
4b2123dd9c [mips] Fix encoding of BAL instruction. Also, fix assembler test case which 
was not catching the error.

llvm-svn: 170953
 2012-12-21 23:13:59 +00:00
Akira Hatanaka
abfa7cf8bf [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
llvm-svn: 170952
 2012-12-21 23:03:50 +00:00
Akira Hatanaka
5fb1ba2c90 [mips] Refactor load/store left/right and load-link and store-conditional 
instructions.

llvm-svn: 170950
 2012-12-21 23:01:24 +00:00
Akira Hatanaka
7e5047d48a [mips] Refactor load/store instructions. 
llvm-svn: 170948
 2012-12-21 22:58:55 +00:00
Akira Hatanaka
282d5fff48 [mips] Remove unnecessary isPseudo parameter. 
llvm-svn: 170947
 2012-12-21 22:57:26 +00:00
Akira Hatanaka
607c79d3a2 [mips] Refactor LUI instruction. 
llvm-svn: 170944
 2012-12-21 22:46:07 +00:00
Akira Hatanaka
5953571624 [mips] Refactor count leading zero or one instructions. 
llvm-svn: 170942
 2012-12-21 22:43:58 +00:00
Akira Hatanaka
aae0730c16 [mips] Refactor sign-extension-in-register instructions. 
llvm-svn: 170940
 2012-12-21 22:41:52 +00:00
Akira Hatanaka
28f3fe9725 [mips] Refactor instructions which copy from and to HI/LO registers. 
llvm-svn: 170939
 2012-12-21 22:39:17 +00:00
Akira Hatanaka
22e49f11a7 [mips] Refactor logical NOR instructions. 
llvm-svn: 170937
 2012-12-21 22:35:47 +00:00
Akira Hatanaka
adbd4c7cba [mips] Move instruction definitions in MipsInstrInfo.td. 
llvm-svn: 170936
 2012-12-21 22:33:43 +00:00
Reed Kotler
4796d835c7 There is one more patch to finish large frames. Make sure we assert 
on code that has large frames which will not yet compile correctly.

llvm-svn: 170673
 2012-12-20 06:57:00 +00:00
Akira Hatanaka
e0e871529a [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 

llvm-svn: 170664
 2012-12-20 04:27:52 +00:00
Akira Hatanaka
0c5b53d93f [mips] Refactor unconditional branch instruction. Separate encoding information 
from the rest. 

llvm-svn: 170663
 2012-12-20 04:22:39 +00:00
Akira Hatanaka
9ed2d54e79 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka
1b980a0268 [mips] Delete definition of CPRESTORE instruction. 
llvm-svn: 170660
 2012-12-20 04:15:30 +00:00
Akira Hatanaka
3266206836 [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka
654c74a52d [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka
4661f12a89 [mips] Change the order of template parameters. Move the default parameters to 
the end. 

llvm-svn: 170651
 2012-12-20 03:52:08 +00:00
Akira Hatanaka
06f2007a02 [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka
c627c88fc5 [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00
Akira Hatanaka
689a2c61b4 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.

llvm-svn: 170648
 2012-12-20 03:40:03 +00:00
Akira Hatanaka
78d41e6181 [mips] Refactor arithmetic and logic instructions. Separate encoding 
information from the rest.

llvm-svn: 170647
 2012-12-20 03:34:05 +00:00
Akira Hatanaka
7d1a8021c6 [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and 
ArithLogicI as the instruction base classes.

llvm-svn: 170642
 2012-12-20 03:00:16 +00:00
Akira Hatanaka
01e48fccff [mips] Move class IsCommutable into MipsInstrInfo.td. 
llvm-svn: 170054
 2012-12-13 00:32:01 +00:00
Akira Hatanaka
bb4c3cdc37 [mips] Delete nodes and instructions for dynamic alloca that are no longer in 
use.

llvm-svn: 169580
 2012-12-07 03:10:18 +00:00
Akira Hatanaka
57161323ed [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Akira Hatanaka
9894b24617 [mips] Remove unnecessary predicates. 
llvm-svn: 169577
 2012-12-07 03:01:24 +00:00
Akira Hatanaka
0f8303f1e5 [mips] Generate big GOT code. 
llvm-svn: 168460
 2012-11-21 20:40:38 +00:00
Akira Hatanaka
ee3532f807 [mips] Add predicate HasFPIdx for floating-point indexed load instruction 
support and use it in place of HasMips32r2Or64.

llvm-svn: 168089
 2012-11-15 21:17:13 +00:00
Akira Hatanaka
1bfa522bfe [mips] Set flag neverHasSideEffects flag on floating point conversion 
instructions.

llvm-svn: 167348
 2012-11-03 00:53:12 +00:00
Akira Hatanaka
61434a3632 [mips] Set flag isAsCheapAsAMove flag on instruction LUi. 
llvm-svn: 167345
 2012-11-03 00:26:02 +00:00
Akira Hatanaka
245eaafd42 [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables 
re-materialization of immediate loads.

llvm-svn: 167153
 2012-10-31 18:37:55 +00:00
Akira Hatanaka
18ec43c9c2 [mips] Fix TAILCALL's operand node type. 
llvm-svn: 166341
 2012-10-19 21:30:15 +00:00
Akira Hatanaka
54f6697369 [mips] Add tail call instructions. 
llvm-svn: 166338
 2012-10-19 21:14:34 +00:00
Akira Hatanaka
8198825482 [mips] Make the branch nodes used in jump instructions a template parameter. 
llvm-svn: 166337
 2012-10-19 21:11:03 +00:00
Akira Hatanaka
cfc486ced3 Add node and enum for mips tail call. 
llvm-svn: 166318
 2012-10-19 20:59:39 +00:00
Jack Carter
f403d95eb4 Initial assembler implementation of Mips load address macro 
This patch provides initial implementation of load address 
macro instruction for Mips. We have implemented two kinds 
of expansions with their variations depending on the size 
of immediate operand:

 1) load address with immediate value directly:
    * la d,j => addiu d,$zero,j   (for -32768 <= j <= 65535)
    * la d,j => lui d,hi16(j)
                ori d,d,lo16(j)   (for any other 32 bit value of j)

 2) load load address with register offset value
    * la d,j(s) => addiu d,s,j     (for -32768 <= j <= 65535)
    * la d,j(s) => lui d,hi16(j)   (for any other 32 bit value of j)
                   ori d,d,lo16(j)
                   addu d,d,s

This patch does not cover the case when the address is loaded 
from the value of the label or function.

Contributer: Vladimir Medic
llvm-svn: 165561
 2012-10-09 23:29:45 +00:00
Jack Carter
c5f946b170 Adding support for instructions mfc0, mfc2, mtc0, mtc2 
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
 2012-10-06 01:17:37 +00:00
Jack Carter
a6d222bf00 Implement methods that enable expansion of load immediate 
macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199
 2012-10-04 04:03:53 +00:00
Akira Hatanaka
804a9036c3 MIPS DSP: add vector load/store patterns. 
llvm-svn: 164744
 2012-09-27 01:50:59 +00:00
Akira Hatanaka
03b00bdf4d Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and 
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960
 2012-09-15 01:52:08 +00:00
Jack Carter
93a95cbdde The Mips standalone assembler aliased instruction support. 
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.

These changes are in the instruction td file.

Test cases included

Contributer: Vladimir Medic
llvm-svn: 163368
 2012-09-07 01:42:38 +00:00
Jakob Stoklund Olesen
4da790818a Add missing SDNPSideEffect flags. 
llvm-svn: 162557
 2012-08-24 14:43:27 +00:00
Akira Hatanaka
4e1b032521 Add stub methods for mips assembly matcher. 
Patch by Vladimir Medic.

llvm-svn: 162124
 2012-08-17 20:16:42 +00:00
Jack Carter
3f30c3effe The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 
were using a class defined for 32 bit instructions and 
thus the instruction was for addiu instead of daddiu.

This was corrected by adding the instruction opcode as a 
field in the  base class to be filled in by the defs.

llvm-svn: 161359
 2012-08-06 23:29:06 +00:00