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Commit Graph

168969 Commits

Author SHA1 Message Date
Jessica Paquette
d1afddc21f Add size remarks to MachineFunctionPass
This adds per-function size remarks to codegen, similar to what we have in the
IR layer as of r341588. This only impacts MachineFunctionPasses.

This does the same thing, but for `MachineInstr`s instead of just
`Instructions`. After this, when a `MachineFunctionPass` modifies the number of
`MachineInstr`s in the function it ran on, you'll get a remark.

To enable this, use the size-info analysis remark as before.

llvm-svn: 341876
2018-09-10 22:24:10 +00:00
Lang Hames
0868909fd3 [ORC] Render unresolved symbol addresses as "<not resolved>" in JITDylib::dump.
This is easier to spot among the real addresses than "0x0000000000000000".

llvm-svn: 341873
2018-09-10 22:09:11 +00:00
Lang Hames
dfc0a90170 [ORC] Simplify LLJIT::Create by removing the ExecutionSession parameter.
The Create method can just construct the ExecutionSession, rather than having the
client pass it in.

llvm-svn: 341872
2018-09-10 22:08:57 +00:00
Craig Topper
4a1689c313 [X89] Explicitly enable aes in aes-schedule.ll to fix failures after r341861.
llvm-svn: 341868
2018-09-10 21:49:01 +00:00
JF Bastien
f2a34da2d5 Fix bit_cast properly
Mismatched braces.

llvm-svn: 341867
2018-09-10 21:43:17 +00:00
JF Bastien
b0e7fe6110 Fix bit_cast __is_trivially_copyable
It's a function-like builtin, not a template.

llvm-svn: 341866
2018-09-10 21:41:14 +00:00
JF Bastien
8c1a74de74 [ADT] bit_cast: check for is_trivially_copyable more portably
Summary:
It turns out that isPodLike isn't a good workaround for is_trivially_copyable for bit_cast's purpose. In D51872 Louis points out that tuple and pair really aren't a good fit, and for bit_cast I want to capture array. This patch instead checks is_trivially_copyable directly in bit_cast for all but GCC 4.x. In GCC 4.x developers only check for sizeof match, which means any mistake they make will succeed locally and fail on the bots. Realistically that's few developers and they'll be left behind once we upgrade past C++11.

This will allow using bit_cast with std::array.

Subscribers: dexonsmith, llvm-commits, ldionne, rsmith

Differential Revision: https://reviews.llvm.org/D51888

llvm-svn: 341865
2018-09-10 21:33:45 +00:00
Zachary Turner
292752110a Re-run clang-format on one file.
clang-format was getting confused due to the presence of a macro
invocation that was not terminated by a semicolon.  Fixed this by
terminating the macro lines with semicolons and re-ran clang-format
on the file.

llvm-svn: 341864
2018-09-10 21:31:21 +00:00
Zachary Turner
0d0bd7c7a5 [PDB] Change uint32_t to SymIndex wherever it makes sense.
Although it's just a typedef, it helps for readability.  NFC.

llvm-svn: 341863
2018-09-10 21:30:59 +00:00
Erich Keane
472468eb88 Move FeatureAES from SLM, WSM and SNB to GLM and SKL
Complements https://reviews.llvm.org/D51510 and matches
https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01940.html

GoldmontProc already has FeatureAES.

Patch By: thiagomacieira

Differential Revision: https://reviews.llvm.org/D51565

llvm-svn: 341861
2018-09-10 21:12:19 +00:00
Craig Topper
2f3805dc2c [X86] Mark the ISD::SETLT/SETLE condition codes as illegal for v32i16/v64i8 to match the other vector types.
I'm having a hard time finding a test case for this, but we should be consistent here. The fact that we canonicalize all zeros and all ones constants to vXi32 and all other constants to loads makes this hard to hit the easy DAG combine infinite loop we get for some of the other types.

llvm-svn: 341859
2018-09-10 20:31:27 +00:00
Stella Stamenova
2dc5ee2dcf [lit] Disable shtest-timeout on Windows
Summary: This is the only test that is still failing on Windows - or rather, it is expected to fail on the bots, but passes on the new bot that we're preparing causing a failure, so I'm going to disable it. Since the test has rarely, if ever, passed on the bots, this should have the same effect and it will unblock the creation of the new bot.

Reviewers: asmith, delcypher, zturner

Subscribers: stella.stamenova, llvm-commits

Differential Revision: https://reviews.llvm.org/D51871

llvm-svn: 341856
2018-09-10 20:24:05 +00:00
Alina Sbirlea
8e13e528fa API to update MemorySSA for cloned blocks and added CFG edges.
Summary:
End goal is to update MemorySSA in all loop passes. LoopUnswitch clones all blocks in a loop. SimpleLoopUnswitch clones some blocks. LoopRotate clones some instructions.
Some of these loop passes also make CFG changes.
This is an API based on what I found needed in LoopUnswitch, SimpleLoopUnswitch, LoopRotate, LoopInstSimplify, LoopSimplifyCFG.
Adding dependent patches using this API for context.

Reviewers: george.burgess.iv, dberlin

Subscribers: sanjoy, jlebar, Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D45299

llvm-svn: 341855
2018-09-10 20:13:01 +00:00
JF Bastien
221f0eeead NFC: bit.h don't warn on strict aliasing for GCC <= 7.1
Summary: Addressed https://bugs.llvm.org/show_bug.cgi?id=38885

Subscribers: dexonsmith, llvm-commits, rsmith, steven_wu, RKSimon, Abhilash, srhines

Differential Revision: https://reviews.llvm.org/D51869

llvm-svn: 341853
2018-09-10 19:56:42 +00:00
Petr Hosek
cb13baddcd [ADT] Support converting to lowercase string in toHex
This is useful in certain use-cases such as D51833.

Differential Revision: https://reviews.llvm.org/D51835

llvm-svn: 341852
2018-09-10 19:34:44 +00:00
Krzysztof Parzyszek
540be5f2de [Hexagon] Split large offsets into properly aligned addends
llvm-svn: 341851
2018-09-10 18:49:16 +00:00
Sanjay Patel
6ec4a8b575 [InstCombine] use SelectInst operand names to make code clearer; NFC
Cleanup step for D51433.

llvm-svn: 341850
2018-09-10 18:37:59 +00:00
Sanjay Patel
2a2e81425b [x86] test codegen for unsigned saturated add; NFC
All of the ISA holes are going to make this difficult,
but we can't canonicalize the IR and try to solve PR14613
until we have backend support to get this right.

https://bugs.llvm.org/show_bug.cgi?id=14613

https://rise4fun.com/Alive/Guv
https://rise4fun.com/Alive/AADG

llvm-svn: 341845
2018-09-10 17:40:15 +00:00
Tatyana Krasnukha
0dc58b1fa0 [ARC] Fix macro usage (DEBUG -> LLVM_DEBUG)
llvm-svn: 341844
2018-09-10 17:09:09 +00:00
Alexander Timofeev
0547c6d3de [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32.
Differential revision: https://reviews.llvm.org/D51586

    Reviewer: rampitec

llvm-svn: 341843
2018-09-10 16:42:49 +00:00
Philip Reames
7578ed61eb [AST] Visit memtransfer arguments in order
The only point to this change is the test diffs.  When I remove this code entirely (in favor of the recently added generic handling), I don't want there to be any confusion due to spurious test diffs.

As an aside, the fact out tests are AST construction order dependent is not great.  I thought about fixing that, but the reasonable schemes I might want (e.g. sort by name) need the test diffs anyways.

Philip

llvm-svn: 341841
2018-09-10 16:00:27 +00:00
Petar Jovanovic
61013536ec [MIPS GlobalISel] Select icmp
Select 32bit integer compare instructions for MIPS32.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D51489

llvm-svn: 341840
2018-09-10 15:56:52 +00:00
Sebastian Pop
970fae9285 HotColdSplitting: fix test failing because of last commit
llvm-svn: 341839
2018-09-10 15:42:17 +00:00
Sebastian Pop
ccc9f17f1f HotColdSplitting: check that target supports cold calling convention
Before tagging a function with coldcc make sure the target supports cold calling
convention. Without this patch HotColdSplitting pass fails on aarch64 with:

  fatal error: error in backend: Unsupported calling convention.

llvm-svn: 341838
2018-09-10 15:08:02 +00:00
Sebastian Pop
4658a91b60 add flag instead of using a constant [NFC]
llvm-svn: 341837
2018-09-10 15:07:59 +00:00
Sebastian Pop
b43ec5a3a5 make flag name more specific to gvn [NFC]
llvm-svn: 341836
2018-09-10 15:07:56 +00:00
Gil Rapaport
4aac29dd0b [LSR] Add tests for small constants; NFC
LSR reassociates small constants that fit into add immediate operands as
unfolded offset. Since unfolded offset is not combined with loop-invariant
registers, LSR does not consider solutions that bump invariant registers by
these constants outside the loop.

llvm-svn: 341835
2018-09-10 14:56:24 +00:00
Tim Northover
0f17fdc4c5 InstCombine: move hasOneUse check to the top of foldICmpAddConstant
There were two combines not covered by the check before now, neither of which
actually differed from normal in the benefit analysis.

The most recent seems to be because it was just added at the top of the
function (naturally). The older is from way back in 2008 (r46687) when we just
didn't put those checks in so routinely, and has been diligently maintained
since.

llvm-svn: 341831
2018-09-10 14:26:44 +00:00
Benjamin Kramer
dc73a4e1f4 [Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation is already
llvm-svn: 341826
2018-09-10 13:55:38 +00:00
Alexandre Ganea
26a9ee8389 [LLD][COFF] Cleanup error messages / add more coverage tests
- Log the reason for a PDB or precompiled-OBJ load failure
- Properly handle out-of-date PDB or precompiled-OBJ signature by displaying a corresponding error
- Slightly change behavior on PDB failure: any subsequent load attempt from another OBJ would result in the same error message being logged
- Slightly change behavior on PDB failure: retry with filename only if previous error was ENOENT ("no such file or directory")
- Tests: a. for native PDB errors; b. cover all the cases above

Differential Revision: https://reviews.llvm.org/D51559

llvm-svn: 341825
2018-09-10 13:51:21 +00:00
Benjamin Kramer
6dd0efd86d [Target] Untangle disassemblers
Disassemblers cannot depend on main target headers. The same is true for
MCTargetDesc, but there's a lot more cleanup needed for that.

llvm-svn: 341822
2018-09-10 12:53:46 +00:00
Benjamin Kramer
f196b4cee0 Don't create a temporary vector of loop blocks just to iterate over them.
Loop's getBlocks returns an ArrayRef.

llvm-svn: 341821
2018-09-10 12:32:06 +00:00
John Brawn
10ecfe9801 [GVN] Invalidate cached info for values replaced by equality propagation
When GVN propagates an equality by replacing one value with another it also
needs to invalidate the cached information for the value being replaced.

Differential Revision: https://reviews.llvm.org/D51218

llvm-svn: 341820
2018-09-10 12:23:05 +00:00
Matt Arsenault
e6ee55b83f AMDGPU: Remove function pointer type hack
Now the pointer size should always be correct and
we don't need to improperly inspect the pointee type.

llvm-svn: 341806
2018-09-10 12:16:11 +00:00
Matt Arsenault
5f0ac3a9ea AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit
This will require something to cast. Before this would eliminate
the cast, which would result in copies of $noreg.

llvm-svn: 341803
2018-09-10 11:59:27 +00:00
Matt Arsenault
8aede5e432 DAG: Handle odd vector sizes in calling conv splitting
This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.

Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.

This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.

llvm-svn: 341801
2018-09-10 11:49:23 +00:00
Simon Pilgrim
73a837ca93 [llvm-exegesis] Ignore double spaced separators in asm strings
Some asm has double spaces between operands, the deserializer was keeping these empty split pieces, causing assertions later on:

'ADC16mi RDI i_0x1x  i_0x0x  i_0x1x'

llvm-svn: 341799
2018-09-10 10:45:04 +00:00
Carl Ritson
d7c0f774c4 [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting
Summary:
This fixes a bug where a large number of implicit def instructions can fill the GCNHazardRecognizer lookahead buffer causing required NOPs to not be inserted.

Reviewers: nhaehnle, arsenm

Reviewed By: arsenm

Subscribers: sheredom, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D51726

Change-Id: Ie75338f94de704ee5816b05afd0c922c6748a95b
llvm-svn: 341798
2018-09-10 10:14:48 +00:00
Hans Wennborg
b70865a352 ReleaseNotes: update links to use https
llvm-svn: 341785
2018-09-10 08:50:31 +00:00
Max Kazantsev
bddb12a8cf [IndVars] Set Changed if rewriteFirstIterationLoopExitValues changes IR. PR38863
Currently, `rewriteFirstIterationLoopExitValues` does not set Changed flag even if it makes
changes in the IR. There is no clear evidence that it can cause a crash, but it
looks highly suspicious and likely invalid.

Differential Revision: https://reviews.llvm.org/D51779
Reviewed By: skatkov

llvm-svn: 341779
2018-09-10 06:50:16 +00:00
Max Kazantsev
c9fa24d06f [IndVars] Set Changed if sinkUnusedInvariants changes IR. PR38863
Currently, `sinkUnusedInvariants` does not set Changed flag even if it makes
changes in the IR. There is no clear evidence that it can cause a crash, but it
looks highly suspicious and likely invalid.

Differential Revision: https://reviews.llvm.org/D51777
Reviewed By: skatkov

llvm-svn: 341777
2018-09-10 06:32:00 +00:00
Vikram TV
bbc52ae47d Move a transformation routine from LoopUtils to LoopVectorize.
Summary:
Move InductionDescriptor::transform() routine from LoopUtils to its only uses in LoopVectorize.cpp.
Specifically, the function is renamed as InnerLoopVectorizer::emitTransformedIndex().

This is a child to D51153.

Reviewers: dmgreen, llvm-commits

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D51837

llvm-svn: 341776
2018-09-10 06:16:44 +00:00
David Carlier
d476466502 [XRay] Fix buildbot failure
llvm-svn: 341774
2018-09-10 05:29:49 +00:00
Vikram TV
d95d133618 Move createMinMaxOp() out of RecurrenceDescriptor.
Reviewers: dmgreen, llvm-commits

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D51838

llvm-svn: 341773
2018-09-10 05:05:08 +00:00
David Carlier
048b971f08 [Xray] tooling allow MachO format support
Getting writable xray __DATA sections from MachO as well.

Reviewers: dberris

Reviewed By: dberris

Differential Revision: https://reviews.llvm.org/D51758

llvm-svn: 341772
2018-09-10 05:00:43 +00:00
Dean Michael Berris
1c078cbefe [XRay] Remove unused reference
The reference was only used in the assertion.

Follow-up on D51723.

llvm-svn: 341771
2018-09-10 02:57:05 +00:00
Matt Arsenault
6815ea5d8c AMDGPU: Fix tests using old number for constant address space
llvm-svn: 341770
2018-09-10 02:54:25 +00:00
Dean Michael Berris
665e1fb24b [XRay] Add a BlockVerifier visitor for FDR Records
Summary:
This patch implements a `BlockVerifier` type which enforces the
invariants of the log structure of FDR mode logs on a per-block basis.
This ensures that the data we encounter from an FDR mode log
semantically correct (i.e. that records follow the documented "grammar"
for FDR mode log records).

This is another part of the refactoring of D50441.

This is a slightly modified version of rL341628, avoiding the
`std::tuple<...>` constructor that is not constexpr in C++11.

Reviewers: mboerger, eizan

Subscribers: mgorny, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D51723

llvm-svn: 341769
2018-09-10 02:35:25 +00:00
Matt Arsenault
ec008a0c57 AMDGPU: Use GOT PSV since it has an address space now
llvm-svn: 341768
2018-09-10 02:23:39 +00:00
Matt Arsenault
be2c74310e AMDGPU: Don't abort on unknown addrspace argument
llvm-svn: 341767
2018-09-10 02:23:30 +00:00