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Commit Graph

20708 Commits

Author SHA1 Message Date
Tom Stellard
d2fff2dd99 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
llvm-svn: 190077
2013-09-05 18:37:52 +00:00
Joey Gouly
e37f727df1 [ARMv8] Add some missing tests for DSB/DMB.
llvm-svn: 190060
2013-09-05 16:05:45 +00:00
Joey Gouly
071ca2ff6d [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Richard Barton
48e8048205 Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.

llvm-svn: 190053
2013-09-05 14:14:19 +00:00
Tilmann Scheller
31cc184566 Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.

llvm-svn: 190047
2013-09-05 11:59:43 +00:00
Tilmann Scheller
14c2ce0a1e ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.

Patch by Daniel Stewart!
   

llvm-svn: 190043
2013-09-05 11:10:31 +00:00
Richard Sandiford
399318ba38 [SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.

llvm-svn: 190041
2013-09-05 10:36:45 +00:00
Venkatraman Govindaraju
b3ea970660 [Sparc] Correctly handle call to functions with ReturnsTwice attribute.
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033
2013-09-05 05:32:16 +00:00
Andrew Trick
330821bce0 mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

llvm-svn: 190014
2013-09-04 23:54:00 +00:00
Eric Christopher
1c6f3e85e7 Remove hack ensuring that darwin didn't produce dwarf > 3 for modules
without a limiting factor.

Update all testcases accordingly.

llvm-svn: 190002
2013-09-04 22:21:24 +00:00
Eric Christopher
fd11e8a82d Expand and rewrite comment.
llvm-svn: 189998
2013-09-04 21:23:23 +00:00
Arnold Schwaighofer
22610acac7 Change swift/vldm test case to be less dependent on allocation order
'Force' values in registers using the calling convention. Now, we only depend on
the calling convention and that the allocator performs copy coalescing.

llvm-svn: 189985
2013-09-04 20:51:06 +00:00
Vincent Lejeune
4fd20e35e6 R600: Use shared op optimization when checking cycle compatibility
llvm-svn: 189981
2013-09-04 19:53:54 +00:00
Vincent Lejeune
4a8c23c168 R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
2013-09-04 19:53:46 +00:00
Vincent Lejeune
95def9718e R600: Remove fmul.v4f32.ll test which is redundant with fmul.ll
llvm-svn: 189978
2013-09-04 19:53:22 +00:00
Rafael Espindola
0a6eda454a Merge these 2 tests in a single file.
llvm-svn: 189975
2013-09-04 19:19:32 +00:00
Arnold Schwaighofer
ac9a5042d8 Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

llvm-svn: 189961
2013-09-04 17:41:16 +00:00
Silviu Baranga
f1ba2ead74 Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact.
llvm-svn: 189958
2013-09-04 17:05:18 +00:00
Rafael Espindola
357980289a Revert "Add r159136 back now that pr13124 has been fixed."
This reverts commit r189886.

I found a corner case where this optimization is not valid:

Say we have a "linkonce_odr unnamed_addr" in two translation units:
* In TU 1 this optimization kicks in and makes it hidden.
* In TU 2 it gets const merged with a constant that is *not* unnamed_addr,
  resulting in a non unnamed_addr constant with default visibility.
* The static linker rules for combining visibility them produce a hidden
  symbol, which is incorrect from the point of view of the non unnamed_addr
  constant.

The one place we can do this is when we know that the symbol is not used from
another TU in the same shared object, i.e., during LTO. I will move it there.

llvm-svn: 189954
2013-09-04 16:09:01 +00:00
Rafael Espindola
da89e5d74e Error on linking appending globals with different unnamed_addr.
llvm-svn: 189950
2013-09-04 15:33:34 +00:00
Venkatraman Govindaraju
30d6d6f6c9 [Sparc] Fix an assertion failure while lowering fcmp on long double.
This assertion is triggered because an integer constant is created with wrong
  type.

llvm-svn: 189948
2013-09-04 15:15:20 +00:00
Rafael Espindola
955b2d5751 Fix linking of unnamed_addr in functions.
llvm-svn: 189945
2013-09-04 14:59:03 +00:00
Rafael Espindola
5fc6c942fa Rename in preparation for adding tests for function linking.
llvm-svn: 189944
2013-09-04 14:40:49 +00:00
Rafael Espindola
8e43d800df Use CHECK-DAG instead of sort.
llvm-svn: 189942
2013-09-04 14:35:48 +00:00
Rafael Espindola
5a6a37f63f Fix linking of unnamed_addr.
This was regression from r134829. When linking we have to be conservative. If
one of the symbols has a significant address, then the result should have it
too.

llvm-svn: 189935
2013-09-04 14:05:09 +00:00
Tim Northover
baf9697e72 InstCombine: allow unmasked icmps to be combined with logical ops
"(icmp op i8 A, B)" is equivalent to "(icmp op i8 (A & 0xff), B)" as a
degenerate case. Allowing this as a "masked" comparison when analysing "(icmp)
&/| (icmp)" allows us to combine them in more cases.

rdar://problem/7625728

llvm-svn: 189931
2013-09-04 11:57:17 +00:00
Tim Northover
9045305fce InstCombine: look for masked compares with subset relation
Even in cases which aren't universally optimisable like "(A & B) != 0 && (A &
C) != 0", the masks can make one of the comparisons completely redundant. In
this case, since we've gone to the effort of spotting masked comparisons we
should combine them.

rdar://problem/7625728

llvm-svn: 189930
2013-09-04 11:57:13 +00:00
Hao Liu
b344ca7aa3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
2013-09-04 09:28:24 +00:00
Michael Gottesman
51a877bd8c Revert "Revert "Remove the darwin gdb option, that version of gdb is now dead and the rest of the compatibility should be done on a dwarf-N level.""
This reverts commit r189913.

Talked with Eric on IRC. I am going to XFAIL the failing test since it
is using what Eric described as "the member hack" which was needed on
that old GDB.

Sorry for the noise!

llvm-svn: 189914
2013-09-04 04:39:38 +00:00
Michael Gottesman
eab573e114 Revert "Remove the darwin gdb option, that version of gdb is now dead and the rest of the compatibility should be done on a dwarf-N level."
This reverts commit r189903.

This commit broke the phase 1 buildbot for a while.

http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RAincremental/builds/6684

llvm-svn: 189913
2013-09-04 04:31:56 +00:00
Eric Christopher
791c6f4134 Remove the darwin gdb option, that version of gdb is now dead and
the rest of the compatibility should be done on a dwarf-N level.

llvm-svn: 189903
2013-09-04 02:02:10 +00:00
Rafael Espindola
8b9c0a576e Add r159136 back now that pr13124 has been fixed.
Original message:
If a constant or a function has linkonce_odr linkage and unnamed_addr, mark
hidden. Being linkonce_odr guarantees that it is available in every dso that
needs it. Being a constant/function with unnamed_addr guarantees that the
copies don't have to be merged.

llvm-svn: 189886
2013-09-03 23:34:36 +00:00
Michael Gottesman
81c7cd8b47 [objc-arc] Turn off the objc_retainBlock -> objc_retain optimization.
The reason that I am turning off this optimization is that there is an
additional case where a block can escape that has come up. Specifically, this
occurs when a block is used in a scope outside of its current scope.

This can cause a captured retainable object pointer whose life is preserved by
the objc_retainBlock to be deallocated before the block is invoked.

An example of the code needed to trigger the bug is:

----
\#import <Foundation/Foundation.h>
int main(int argc, const char * argv[]) {
  void (^somethingToDoLater)();

  {
    NSObject *obj = [NSObject new];

    somethingToDoLater = ^{
      [obj self]; // Crashes here
    };
  }

  NSLog(@"test.");

  somethingToDoLater();
  return 0;
}
----

In the next commit, I remove all the dead code that results from this.

Once I put in the fixing commit I will bring back the tests that I deleted in
this commit.

rdar://14802782.
rdar://14868830.

llvm-svn: 189869
2013-09-03 22:40:54 +00:00
Michael Gottesman
6bf22747af [objc-arc] Move some block tests from basic.ll -> retain-block.ll and add some missing CHECK-LABELS.
llvm-svn: 189868
2013-09-03 22:40:50 +00:00
Matt Arsenault
469d672381 Teach InstCombineLoadCast about address spaces.
This is another one that doesn't matter much,
but uses the right GEP index types in the first
place.

llvm-svn: 189854
2013-09-03 21:05:48 +00:00
Jim Grosbach
4f219b5c7e Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
This reverts commit r189648.

Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.

llvm-svn: 189841
2013-09-03 20:08:17 +00:00
Eric Christopher
423b50bc11 Add the rest of the stock attributes to the attribute table.
This won't affect the kinds of hashes we test for as we actually
do hashing based on form and attribute. Change the fission-hash
testcase one last time to handle DW_AT_comp_dir.

llvm-svn: 189840
2013-09-03 20:00:20 +00:00
Yi Jiang
e1b34bf1fe In this patch we are trying to do two things:
1) If the width of vectorization list candidate is bigger than vector reg width, we will break it down to fit the vector reg.
2) We do not vectorize the width which is not power of two.

The performance result shows it will help some spec benchmarks. mesa improved 6.97% and ammp improved 1.54%. 

llvm-svn: 189830
2013-09-03 17:26:04 +00:00
Joerg Sonnenberger
930841271b Print string value for DT_RPATH and DT_RUNPATH.
llvm-svn: 189829
2013-09-03 17:13:53 +00:00
Richard Sandiford
2543e2b36c [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now this just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189819
2013-09-03 15:38:35 +00:00
Evgeniy Stepanov
475b9bd212 [msan] Fix handling of select with struct arguments.
llvm-svn: 189796
2013-09-03 13:05:29 +00:00
Evgeniy Stepanov
af50498a8a [msan] Fix select instrumentation.
Select condition shadow was being ignored resulting in false negatives.
This change OR-s sign-extended condition shadow into the result shadow.

llvm-svn: 189785
2013-09-03 10:04:11 +00:00
Venkatraman Govindaraju
ab95772300 [Sparc] Add support for soft long double (fp128).
llvm-svn: 189780
2013-09-03 04:11:59 +00:00
Venkatraman Govindaraju
eaf96576da [Sparc] Implement spill and load for long double(f128) registers.
llvm-svn: 189768
2013-09-02 18:32:45 +00:00
Tilmann Scheller
e8598ae406 ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189766
2013-09-02 17:09:01 +00:00
Tilmann Scheller
9205705478 Revert 189756 for now, it doesn't match what rdar://14871821 really wants.
What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. 

llvm-svn: 189763
2013-09-02 15:48:17 +00:00
Tilmann Scheller
9e0d3ff678 ARM: Default to Swift when compiling for iOS 6 or later.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189756
2013-09-02 12:01:58 +00:00
NAKAMURA Takumi
26f34484dd FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).
llvm-svn: 189755
2013-09-02 12:00:53 +00:00
NAKAMURA Takumi
6f2ef5f35a llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresponding to Craig's r189742.
AMD Piledriver builder detected failures.

llvm-svn: 189754
2013-09-02 12:00:46 +00:00
Craig Topper
6009a9c268 Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
llvm-svn: 189742
2013-09-02 07:53:17 +00:00