Reid Spencer
490c23de9b
Prevent the -pedantic option from causing Mac OS/X build problems:
...
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'
llvm-svn: 28620
2006-06-01 06:12:21 +00:00
Reid Spencer
94a443bb29
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
Evan Cheng
5b6029f577
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
Evan Cheng
6a09baaff4
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
Evan Cheng
bbc183c90e
visitVBinOp: Can't fold divide by zero!
...
llvm-svn: 28584
2006-05-31 06:08:35 +00:00
Evan Cheng
ae1c91ec10
Make sure the register pressure reduction schedulers work for non-uniform
...
latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
Evan Cheng
7e0c2d106e
When a priority_queue is empty, the behavior of top() operator is
...
non-deterministic. Returns NULL when it's empty!
llvm-svn: 28560
2006-05-30 18:04:34 +00:00
Chris Lattner
d8bd52bfd2
Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!):
...
SimplifySelectOps would eliminate a Select, delete it, then return true.
The clients would see that it did something and return null.
The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.
The fix is simple: clients of SimplifySelectOps should return the select
node itself.
In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted. We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.
llvm-svn: 28514
2006-05-27 00:43:02 +00:00
Evan Cheng
58bfb4e600
Make CALL node consistent with RET node. Signness of value has type MVT::i32
...
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
llvm-svn: 28511
2006-05-26 23:13:20 +00:00
Evan Cheng
f53c4cc192
Change RET node to include signness information of the return values. e.g.
...
RET chain, value1, sign1, value2, sign2
llvm-svn: 28509
2006-05-26 23:09:09 +00:00
Evan Cheng
328b47bc28
Remove a bogus cast.
...
llvm-svn: 28492
2006-05-26 08:00:14 +00:00
Evan Cheng
6fdd4960aa
Turn on -sched-commute-nodes by default.
...
llvm-svn: 28465
2006-05-25 08:37:31 +00:00
Evan Cheng
920d9c86f1
CALL node change: now including signness of every argument.
...
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
Chris Lattner
f604017e47
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
Evan Cheng
6909147763
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
Vladimir Prus
125917432a
Fix missing include
...
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
Evan Cheng
19e9e63dcd
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
Evan Cheng
00c1318055
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
Chris Lattner
b2ecc1b1e7
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
Chris Lattner
924f3fed13
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
Evan Cheng
00f391f87b
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
Chris Lattner
4252704561
When we legalize target nodes, do not use getNode to create a new node,
...
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.
This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.
llvm-svn: 28348
2006-05-17 18:00:08 +00:00
Chris Lattner
d3ff015877
Add an assertion, avoid some unneeded work for each call. No functionality
...
change.
llvm-svn: 28347
2006-05-17 17:55:45 +00:00
Chris Lattner
30f61c8bb1
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
Chris Lattner
01f4f28837
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
Andrew Lenharth
14504c85ed
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
Chris Lattner
ba1dfc1da7
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
Chris Lattner
fdd62b9073
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
Chris Lattner
fa068a16e1
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
Chris Lattner
b79e3f7155
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
Evan Cheng
489f9bd68f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
Evan Cheng
7bb257e178
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
Chris Lattner
c439f96b2c
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
Evan Cheng
772647518f
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
Chris Lattner
9e29384a4b
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
Chris Lattner
9a24639afc
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
Chris Lattner
11064741d3
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
Chris Lattner
474e1b7ef3
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
Chris Lattner
90527550c1
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
Chris Lattner
db5b91f6a8
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
Owen Anderson
29e4d70aed
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
Evan Cheng
f3d7bb7a9e
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
Evan Cheng
c24d0f281c
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
Chris Lattner
a500852895
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
Evan Cheng
0b8e4bca80
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
Evan Cheng
cb2a0f392c
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
Evan Cheng
7028ff2e25
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
Evan Cheng
da04c3aab4
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
Evan Cheng
03fa9eb65e
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
Evan Cheng
9f269c1bef
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
Nate Begeman
3af196c9b2
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
Chris Lattner
486e0660b7
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
Evan Cheng
1a8feb189e
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
Evan Cheng
3f72d2121b
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
Evan Cheng
aad3fe008e
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
Chris Lattner
b7152b0b42
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
Chris Lattner
28fe830b3b
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
Chris Lattner
d2aea9851e
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
Chris Lattner
830bed591e
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
Chris Lattner
baefeb1e09
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
Chris Lattner
6ede576b55
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
Chris Lattner
f45b6d5c08
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
Chris Lattner
eed10e837c
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
Chris Lattner
7b8a0cfff3
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
Chris Lattner
4f66de151c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
Chris Lattner
bbe4393bc4
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
Nate Begeman
1f359b07de
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
Nate Begeman
b8e351aec5
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
Chris Lattner
f76c0b6662
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
Chris Lattner
4a4cbde0bb
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
Chris Lattner
3d5d01a74b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
Jeff Cohen
248e133255
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
Chris Lattner
ca06e2522e
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
Chris Lattner
02d3258820
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
Chris Lattner
32e96402c0
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
Chris Lattner
c912cf0b07
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
Chris Lattner
06cb36074a
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
Chris Lattner
4b581e4167
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
Chris Lattner
229d3e3c2d
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
Chris Lattner
d7637651b6
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
Chris Lattner
584874682a
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
Chris Lattner
bec98440f4
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
Chris Lattner
02bb78abd3
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
Chris Lattner
53e8cbbb83
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
Jeff Cohen
953baf0494
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
Chris Lattner
56694d0bb0
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
Chris Lattner
db888e7880
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
Evan Cheng
ceb7645d40
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
Chris Lattner
32adc4592f
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
Chris Lattner
075404adaa
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
Chris Lattner
685568510a
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
Chris Lattner
51b0cac238
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
Chris Lattner
a39a7f900f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
Chris Lattner
c779fca289
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
Chris Lattner
ed58ec2a57
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
Chris Lattner
0f89e6b11d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
Chris Lattner
d36b66d6dc
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
Nate Begeman
95a4f191e0
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
Evan Cheng
2922daab4b
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
Owen Anderson
71bc529dfa
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Chris Lattner
06ccac43d7
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
Chris Lattner
2bf37af52d
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
Chris Lattner
8054cd3830
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
Chris Lattner
055baf5c7b
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
Nate Begeman
2a81b6be22
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
Chris Lattner
5c1abc2b94
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
Chris Lattner
bb8c8b5d9d
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
Nate Begeman
05174045df
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
Jeff Cohen
a35a8a5f9c
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
Jeff Cohen
b257253098
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
Jeff Cohen
ec0f5808a1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
Chris Lattner
c2914c8ac5
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
Chris Lattner
a9f3c7c50a
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
Chris Lattner
befcd1e76d
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
Evan Cheng
44e851f6ec
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
Evan Cheng
494e47d755
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
Evan Cheng
94264c7c90
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
Evan Cheng
ef706b77c4
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
Chris Lattner
bce271e829
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
Evan Cheng
02e72f8f55
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
Chris Lattner
6ce6942d21
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
Evan Cheng
9f21c2daf4
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
Evan Cheng
f843942504
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
Chris Lattner
4e783a3101
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
Evan Cheng
ff5a88b62e
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
Chris Lattner
85a24e23a2
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
Evan Cheng
a6081bc674
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
Chris Lattner
3b27c1bd33
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
...
PR748.
llvm-svn: 27987
2006-04-27 05:01:07 +00:00
Evan Cheng
b54140b0d6
Don't forget return void.
...
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
Nate Begeman
7bb910dbe7
Fix the updating of the machine CFG when a PHI node was in a successor of
...
the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
llvm-svn: 27952
2006-04-23 06:26:20 +00:00
Nate Begeman
f86709e9e2
Code cleanup associated with jump tables, thanks to Chris for noticing
...
these.
llvm-svn: 27950
2006-04-22 23:52:35 +00:00
Nate Begeman
6cfb33a42c
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
Nate Begeman
7ed816f900
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Chris Lattner
8f7c394f3a
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
Chris Lattner
3b9a7570cb
Fix a couple more memory issues
...
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
Chris Lattner
2ae3ed5e1a
Fix a really subtle and obnoxious memory bug that caused issues with an
...
llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).
llvm-svn: 27922
2006-04-20 23:55:59 +00:00
Chris Lattner
04a8496ef0
This field no longer exists
...
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
Chris Lattner
a6a6ac15af
Remove some of the obvious V9-specific cruft
...
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
Evan Cheng
618314ed2f
Turn a VAND into a VECTOR_SHUFFLE is applicable.
...
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.
llvm-svn: 27874
2006-04-20 08:56:16 +00:00
Chris Lattner
fa2e364d9c
Implement folding of a bunch of binops with undef
...
llvm-svn: 27863
2006-04-20 05:39:12 +00:00
Chris Lattner
a1cf724536
Simplify some code
...
llvm-svn: 27846
2006-04-19 23:17:50 +00:00
Chris Lattner
8c8f1e35c9
Fix handling of calls in functions that use vectors. This fixes a crash on
...
the code in GCC PR26546.
llvm-svn: 27780
2006-04-17 22:10:08 +00:00
Chris Lattner
5f5a9cc8ea
Add a MachineInstr::eraseFromParent convenience method.
...
llvm-svn: 27775
2006-04-17 21:35:41 +00:00
Chris Lattner
9bcfa7f378
Codegen insertelement with constant insertion points as scalar_to_vector
...
and a shuffle. For this:
void %test2(<4 x float>* %F, float %f) {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
%tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
%tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2]
%tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1]
store <4 x float> %tmp6, <4 x float>* %F
ret void
}
we now get this on X86 (which will get better):
_test2:
movl 4(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, %xmm1
shufps $3, %xmm1, %xmm1
movaps %xmm0, %xmm2
shufps $1, %xmm2, %xmm2
unpcklps %xmm1, %xmm2
movss 8(%esp), %xmm1
unpcklps %xmm1, %xmm0
unpcklps %xmm2, %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
ret
instead of:
_test2:
subl $28, %esp
movl 32(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%esp)
movss 36(%esp), %xmm0
movss %xmm0, 8(%esp)
movaps (%esp), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
addl $28, %esp
ret
llvm-svn: 27765
2006-04-17 19:21:01 +00:00
Chris Lattner
c2f3923b63
Add support for promoting stores from one legal type to another, allowing us
...
to write one pattern for vector stores instead of 4.
llvm-svn: 27730
2006-04-16 01:36:45 +00:00
Chris Lattner
918dbf7203
Make these predicates return true for bit_convert(buildvector)'s as well as
...
buildvectors.
llvm-svn: 27723
2006-04-15 23:38:00 +00:00
Chris Lattner
8882bef982
Make this assertion better
...
llvm-svn: 27695
2006-04-14 06:08:35 +00:00
Reid Spencer
4719e9699d
Expand some code with temporary variables to rid ourselves of the warning
...
about "dereferencing type-punned pointer will break strict-aliasing rules"
llvm-svn: 27671
2006-04-13 18:29:58 +00:00
Evan Cheng
1477d2d08f
Promote vector AND, OR, and XOR
...
llvm-svn: 27632
2006-04-12 21:20:24 +00:00
Evan Cheng
ce4e1c0068
Vector type promotion for ISD::LOAD and ISD::SELECT
...
llvm-svn: 27606
2006-04-12 16:33:18 +00:00
Chris Lattner
70d68fcfcb
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
Chris Lattner
3df4b4ca55
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
llvm-svn: 27602
2006-04-12 03:25:41 +00:00
Evan Cheng
be9f313cd8
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
llvm-svn: 27586
2006-04-11 06:33:39 +00:00
Chris Lattner
651f0655d0
add some todos
...
llvm-svn: 27580
2006-04-11 02:00:08 +00:00
Chris Lattner
d02e72ffc3
Add basic support for legalizing returns of vectors
...
llvm-svn: 27578
2006-04-11 01:31:51 +00:00
Jim Laskey
54dc261ef6
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
Evan Cheng
d333e6853c
Missing break
...
llvm-svn: 27559
2006-04-10 18:54:36 +00:00
Chris Lattner
2c57f7285e
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
Chris Lattner
9e4a289fae
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
llvm-svn: 27533
2006-04-08 05:34:25 +00:00
Chris Lattner
fc546e1780
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
Chris Lattner
12c1bd4cbc
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
llvm-svn: 27528
2006-04-08 04:13:17 +00:00
Evan Cheng
375bec1961
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
llvm-svn: 27517
2006-04-08 01:46:37 +00:00
Chris Lattner
234481e1ba
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
Jim Laskey
bec0d42d8d
Remove section change in function end, preventing override of function's real
...
section.
llvm-svn: 27503
2006-04-08 00:35:59 +00:00
Jim Laskey
fabb0ba736
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
Jim Laskey
b93bc75add
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
Evan Cheng
e5eefd369a
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
llvm-svn: 27472
2006-04-06 23:20:43 +00:00
Chris Lattner
fe2926cf46
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
Evan Cheng
abd8dc54c2
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
llvm-svn: 27432
2006-04-05 06:07:11 +00:00
Chris Lattner
cad2bfa3d7
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
llvm-svn: 27402
2006-04-04 17:39:18 +00:00
Chris Lattner
136a27d0d0
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
llvm-svn: 27399
2006-04-04 17:23:26 +00:00
Chris Lattner
85dc06c29e
Constant fold bitconvert(undef)
...
llvm-svn: 27391
2006-04-04 01:02:22 +00:00
Chris Lattner
4601b86ad0
The stack alignment is now computed dynamically, just verify it is correct.
...
llvm-svn: 27380
2006-04-03 21:39:57 +00:00
Chris Lattner
264e4a438a
Remove unused method
...
llvm-svn: 27379
2006-04-03 21:39:03 +00:00
Chris Lattner
d13dd8ef5c
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
llvm-svn: 27375
2006-04-03 17:29:28 +00:00
Chris Lattner
d9902c3de0
Add a missing check, which broke a bunch of vector tests.
...
llvm-svn: 27374
2006-04-03 17:21:50 +00:00
Andrew Lenharth
b133e47444
back this out
...
llvm-svn: 27367
2006-04-03 03:16:50 +00:00
Andrew Lenharth
91c6f28ad6
This should be a win of every arch
...
llvm-svn: 27364
2006-04-02 21:42:45 +00:00
Chris Lattner
dbdc830c83
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
llvm-svn: 27356
2006-04-02 06:11:11 +00:00
Chris Lattner
c76f9e8691
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.
...
llvm-svn: 27349
2006-04-02 05:06:04 +00:00
Chris Lattner
f15063eadf
Implement the Expand action for binary vector operations to break the binop
...
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
llvm-svn: 27347
2006-04-02 03:57:31 +00:00
Chris Lattner
389e309bfb
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
llvm-svn: 27346
2006-04-02 03:41:14 +00:00
Chris Lattner
104db817c8
Constant fold all of the vector binops. This allows us to compile this:
...
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256, r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256, r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
llvm-svn: 27343
2006-04-02 03:25:57 +00:00
Chris Lattner
badebf1c9b
Add a new -view-legalize-dags command line option
...
llvm-svn: 27342
2006-04-02 03:07:27 +00:00
Chris Lattner
52732a272f
Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.
...
llvm-svn: 27341
2006-04-02 02:53:43 +00:00
Chris Lattner
8a66373ad7
These entries already exist
...
llvm-svn: 27340
2006-04-02 02:51:27 +00:00
Chris Lattner
5eefd8e0b3
Add some missing node names
...
llvm-svn: 27339
2006-04-02 02:41:18 +00:00
Chris Lattner
13e8d5973c
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
2006-04-02 00:24:45 +00:00
Chris Lattner
b088cfc01a
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
...
llvm-svn: 27317
2006-03-31 22:16:43 +00:00
Chris Lattner
774bdd598c
Do not endian swap split vector loads. This fixes UnitTests/Vector/sumarray-dbl on PPC.
...
Now all UnitTests/Vector/* tests pass on PPC.
llvm-svn: 27299
2006-03-31 18:22:37 +00:00
Chris Lattner
ffa44397a5
Do not endian swap the operands to a store if the operands came from a vector.
...
This fixes UnitTests/Vector/simple.c with altivec.
llvm-svn: 27298
2006-03-31 18:20:46 +00:00
Chris Lattner
0e7da656a7
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
...
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
llvm-svn: 27297
2006-03-31 18:10:41 +00:00
Chris Lattner
c3be332547
Delete dead loads in the dag. This allows us to compile
...
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
llvm-svn: 27296
2006-03-31 18:06:18 +00:00
Chris Lattner
9d379a4ef3
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
...
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
llvm-svn: 27294
2006-03-31 17:55:51 +00:00
Chris Lattner
e05a1ec544
Scalarized vector stores need not be legal, e.g. if the vector element type
...
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
llvm-svn: 27293
2006-03-31 17:37:22 +00:00
Chris Lattner
f30369b9b1
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
Chris Lattner
82a0e17dd7
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
Evan Cheng
873c48a51a
Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;
...
llvm-svn: 27274
2006-03-31 01:27:51 +00:00