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Commit Graph

139714 Commits

Author SHA1 Message Date
Justin Bogner
d4e3f0bc43 Support: Annotate Error and Expected<> with LLVM_NODISCARD
It's always a mistake to ignore return values with Error or Expected
types.

llvm-svn: 284884
2016-10-21 21:01:12 +00:00
Bob Haarman
a8a5b28981 fixed typo in InstrProf.h; NFC
llvm-svn: 284880
2016-10-21 20:38:37 +00:00
Justin Lebar
61678ad735 [ADT] Get rid of use of LLVM_NOEXCEPT in CachedHashString.h.
LLVM_NOEXCEPT is no longer necessary (yay).

llvm-svn: 284876
2016-10-21 20:28:00 +00:00
Tom Stellard
bbc3abcc55 AMDGPU/SI: Fix crash caused by r284267
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D25782

llvm-svn: 284875
2016-10-21 20:25:11 +00:00
Sanjay Patel
5dbf39179f [DAG] enhance computeKnownBits to handle SHL with vector splat constant
Also, use APInt to avoid crashing on types larger than vNi64.

llvm-svn: 284874
2016-10-21 20:16:27 +00:00
Justin Lebar
fe92dce0bb [ADT] Compare strings' hashes first before comparing their values.
Summary:
We already have the hashes in hand, and comparing hashes should be much
more discriminatory than comparing the StringRefs' sizes.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25705

llvm-svn: 284872
2016-10-21 20:10:51 +00:00
Justin Lebar
d3f769120c [ADT] Add CachedHashString.
Summary:
This is like CachedHashStringRef, but owns its data.

This lets us use strings inside of DenseMaps.

Reviewers: timshen

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25645

llvm-svn: 284871
2016-10-21 20:10:48 +00:00
Justin Lebar
410593c819 [IR] Add DenseMapInfo<CallSite>.
Summary:
A CallSite is basically an Instruction*, and you can put Instruction*s
into DenseMaps, so you should be able to do the same with CallSites.

This is used in a later patch.

Reviewers: timshen

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25643

llvm-svn: 284870
2016-10-21 20:10:44 +00:00
Li Huang
6f568d5434 [SCEV] Memoize visitMulExpr results in SCEVRewriteVisitor.
Summary:
When SCEVRewriteVisitor traverses the SCEV DAG, it may visit the same SCEV
multiple times if this SCEV is referenced by multiple other SCEVs. This has
exponential time complexity in the worst case. Memoizing the results will
avoid re-visiting the same SCEV. Add a map to save the results, and override
the visit function of SCEVVisitor. Now SCEVRewriteVisitor only visit each
SCEV once and thus returns the same result for the same input SCEV.

This patch fixes PR18606, PR18607.

Reviewers: Sanjoy Das, Mehdi Amini, Michael Zolotukhin

Differential Revision: https://reviews.llvm.org/D25810

llvm-svn: 284868
2016-10-21 20:05:21 +00:00
Kevin Enderby
432f0c8446 Fix a bug in the code of llvm-cxxdump in dumpArchive() when
iterating over an archive with object and non-object members that
would cause an Abort because to was not calling consumeError()
when the code was wanting to ignore a non-object file.

Found by Justin Bogner!

llvm-svn: 284867
2016-10-21 20:03:14 +00:00
Kostya Serebryany
143de97a28 [libFuzzer] mention one more trophie
llvm-svn: 284866
2016-10-21 20:01:45 +00:00
Peter Collingbourne
cec8c686b3 Analysis: Move llvm::getConstantRangeFromMetadata to IR library.
We're about to start using it there.

Differential Revision: https://reviews.llvm.org/D25877

llvm-svn: 284865
2016-10-21 19:59:26 +00:00
Peter Collingbourne
1d5e23a582 X86: Improve BT instruction selection for 64-bit values.
If a 64-bit value is tested against a bit which is known to be in the range
[0..31) (modulo 64), we can use the 32-bit BT instruction, which has a slightly
shorter encoding.

Differential Revision: https://reviews.llvm.org/D25862

llvm-svn: 284864
2016-10-21 19:57:55 +00:00
Simon Pilgrim
7f8a590289 [X86][AVX512BWVL] Added support for lowering v16i16 shuffles to AVX512BWVL vpermw
llvm-svn: 284863
2016-10-21 19:54:38 +00:00
Bob Haarman
dd13c8dd0b [pdb] added support for dumping globals stream
Summary: This adds support for dumping the globals stream from PDB files using llvm-pdbdump, similar to the support we have for the publics stream.

Reviewers: ruiu, zturner

Subscribers: beanz, mgorny, modocache

Differential Revision: https://reviews.llvm.org/D25801

llvm-svn: 284861
2016-10-21 19:43:19 +00:00
Simon Pilgrim
dc55ada824 [X86][AVX512BWVL] Added support for combining target v16i16 shuffles to AVX512BWVL vpermw
llvm-svn: 284860
2016-10-21 19:40:29 +00:00
Simon Pilgrim
dd8d6ffe96 [X86][AVX512] Added support for combining target shuffles to AVX512 vpermpd/vpermq/vpermps/vpermd/vpermw
llvm-svn: 284858
2016-10-21 19:18:09 +00:00
Krzysztof Parzyszek
d6f2769360 [RDF] Use RegisterId typedef more consistently, NFC
llvm-svn: 284857
2016-10-21 19:12:13 +00:00
Anna Thomas
0e0d440281 [StripGCRelocates] New pass to remove gc.relocates added by RS4GC
Summary:
Utility pass to remove gc.relocates created by rewrite statepoints for GC.
With respect to safepoint verification, the IR generated would be incorrect, and cannot run
as such.

This would be a single transformation on the final optimized IR.
The benefit of the pass is for easy analysis when the IRs are 'polluted' by too
many gc.relocates.
Added tests.

test run: All RS4GC tests with -verify option. Local downstream tests on large
IR files. This also works when the pointer being gc.relocated is another
gc.relocate.

Reviewers: sanjoy, reames

Subscribers: beanz, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D25096

llvm-svn: 284855
2016-10-21 18:43:16 +00:00
Kevin Enderby
73382bacd0 For llvm-objdump for Mach-O files add printing of
the ARM_THREAD_STATE in the same format as
otool-classic(1) on darwin.

Also remove an extra space in printing the initprot to make
the output match otool-classic(1) on darwin.

rdar://28851457

llvm-svn: 284852
2016-10-21 18:22:35 +00:00
Sanjay Patel
892e568ce5 [DAG] fold negation of sign-bit
0 - X --> 0, if the sub is NUW
0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW
0 - X --> X, if X is 0 or the minimum signed value

This is the DAG equivalent of:
https://reviews.llvm.org/rL284649

plus the fold for the NUW case which already existed in InstSimplify.

Note that we miss a vector fold because of a deficiency in the DAG version of
computeKnownBits().

llvm-svn: 284844
2016-10-21 17:24:26 +00:00
Sanjay Patel
da0a21743a [x86] add tests for potential negation folds
These are the backend equivalents for the tests added in r284627.
The patterns may emerge late, so we should have folds for these in the DAG too.

llvm-svn: 284842
2016-10-21 16:56:29 +00:00
Krzysztof Parzyszek
18cf3c16d9 [Hexagon] Handle spills of partially defined double vector registers
After register allocation it is possible to have a spill of a register
that is only partially defined. That in itself it fine, but creates a
problem for double vector registers. Stores of such registers are pseudo
instructions that are expanded into pairs of individual vector stores,
and in case of a partially defined source, one of the stores may use
an entirely undefined register. To avoid this, track the defined parts
and only generate actual stores for those.

llvm-svn: 284841
2016-10-21 16:38:29 +00:00
Derek Schuff
8f7a717a1c [WebAssembly] Fix for 0xc call_indirect changes
Summary:
Need to reorder the operands to have the callee as the last argument.
Adds a pseudo-instruction, and a pass to lower it into a real
call_indirect.

This is the first of two options for how to fix the problem.

Reviewers: dschuff, sunfish

Subscribers: jfb, beanz, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D25708

llvm-svn: 284840
2016-10-21 16:38:07 +00:00
Abderrazek Zaafrani
6a092a71c6 Set the vectorizer MaxInterleaveFactor for Exynos.
llvm-svn: 284839
2016-10-21 16:28:27 +00:00
Reid Kleckner
17deeccb8f Fix -Wunused-variable warning in libFuzzer
llvm-svn: 284838
2016-10-21 16:26:27 +00:00
Simon Pilgrim
66a5e3ccb8 [X86][SSE] Regenerated sext/zext constant folding tests and added i686 tests
llvm-svn: 284837
2016-10-21 16:22:16 +00:00
Simon Pilgrim
f5c4b15e16 [X86] Use DAG::getBuildVector helper wrapper where possible. NFCI.
llvm-svn: 284835
2016-10-21 16:07:51 +00:00
Konstantin Zhuravlyov
a39632c190 [MachineMemOperand][AtomicSDNode] Remove getSuccessOrdering()
Differential Revision: https://reviews.llvm.org/D25786

llvm-svn: 284834
2016-10-21 16:02:35 +00:00
Simon Pilgrim
d0c57f3341 [X86][SSE] Regenerated chained pmovsx store tests and added i686 tests
llvm-svn: 284833
2016-10-21 15:51:24 +00:00
Abderrazek Zaafrani
dd8173f5ff Test commit
llvm-svn: 284832
2016-10-21 15:24:08 +00:00
Artur Pilipenko
d79ec47437 [LVI] Fix a bug with a guard being the very first instruction in a BB not taken into account
While looking for guards use reverse iterator and scan up to rend() not to begin()

llvm-svn: 284827
2016-10-21 15:02:21 +00:00
Sanjay Patel
1062e6a3e9 fix variable names; NFCI
Because we're just 'or-ing' these 2 variables later in the code, I
don't think there's a logical bug here, but of course the string with
"no size" is the one that should have the size suffix stripped off.

llvm-svn: 284826
2016-10-21 14:58:30 +00:00
Artem Tamazov
ce7f050fe8 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

llvm-svn: 284825
2016-10-21 14:49:22 +00:00
Sanjay Patel
80150ed05d [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds
As discussed in D24815, let's start the process of killing off the broken fast-math global
state housed in TargetOptions and eliminate the need for function-level fast-math attributes.

Here we enable two similar folds that are possible when we don't care about signed-zero:
fadd nsz x, 0 --> x
fsub nsz 0, x --> -x

Note that although the test cases include a 'sin' function call, I'm side-stepping the 
FMF-on-calls question (and lack of support in the DAG) for now. It's not needed for these
tests - isNegatibleForFree/GetNegatedExpression just look through a ISD::FSIN node.

Also, when we create an FNEG node and propagate the Flags of the FSUB to it, this doesn't
actually do anything today because Flags are silently dropped for any node that is not a
binary operator.

Differential Revision: https://reviews.llvm.org/D25297

llvm-svn: 284824
2016-10-21 14:36:58 +00:00
Simon Pilgrim
da9223b586 [X86][AVX2] Begun generalizing lowering to VPERMD/VPERMPS in preparation for AVX512 support.
llvm-svn: 284823
2016-10-21 13:00:47 +00:00
Simon Pilgrim
ef32c05524 Wdocumentation fix
llvm-svn: 284822
2016-10-21 12:51:16 +00:00
Simon Pilgrim
eded0974e0 [X86][AVX512] Add mask/maskz writemask support to subvector broadcast shuffle decode comments
llvm-svn: 284821
2016-10-21 12:14:24 +00:00
John Brawn
c944a4af03 [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops
When we have a loop with a known upper bound on the number of iterations, and
furthermore know that either the number of iterations will be either exactly
that upper bound or zero, then we can fully unroll up to that upper bound
keeping only the first loop test to check for the zero iteration case.

Most of the work here is in plumbing this 'max-or-zero' information from the
part of scalar evolution where it's detected through to loop unrolling. I've
also gone for the safe default of 'false' everywhere but howManyLessThans which
could probably be improved.

Differential Revision: https://reviews.llvm.org/D25682

llvm-svn: 284818
2016-10-21 11:08:48 +00:00
Simon Pilgrim
9c92b4031f [X86][AVX] Add 32-bit target tests for vector lzcnt/tzcnt to demonstrate missed folding opportunities
llvm-svn: 284816
2016-10-21 10:50:52 +00:00
Bjorn Pettersson
1d059f723a [AArch64] Corrected spill size for DDD register class. NFCI
Summary:
The spill size was incorrectly set to 196 bits,
which isn't a multiple of 8. This problem was detected when
experimenting with asserts that the spill size should be a
multiple of the byte size.

New corrected value for the spill size is set to 192 bits.

Note that tablegen (RegisterInfoEmitter) will divide the
size set in the RegisterClass definition by 8. So this
change should not have any impact on the tablegen output
(trunc(192/8) == trunc(196/8) == 24 bytes).

Reviewers: t.p.northover

Subscribers: llvm-commits, aemerson, rengolin

Differential Revision: https://reviews.llvm.org/D25818

llvm-svn: 284814
2016-10-21 09:53:42 +00:00
Benjamin Kramer
2d0f1dea5c Fix WebAssembly test after r284757.
The change to MachineSink shuffles code around, disable it.

llvm-svn: 284813
2016-10-21 09:51:41 +00:00
Benjamin Kramer
45f4714955 [Support] Fix AlignOf test on i386-linux.
On i386 alignof(double) = 8 is not the same as alignof(struct { double
}) = 4. This used to be not an issue because the old implementation
always measured alignment inside of structs. Wrap a dummy struct around
the test to avoid this issue.

llvm-svn: 284812
2016-10-21 09:15:57 +00:00
Craig Topper
27f3f51e3c [AVX-512] Add tests to show opportunities for commuting vpermi2/vpermt2 instructions.
Commuting will be added in a future commit.

llvm-svn: 284808
2016-10-21 05:55:40 +00:00
Davide Italiano
d7b3d1566d Revert "[GVN/PRE] Hoist global values outside of loops."
There's no agreement about this patch. I personally find the
PRE machinery of the current GVN hard enough to reason about
that I'm not sure I'll try to land this again, instead of working
on the rewrite).

llvm-svn: 284796
2016-10-21 01:37:02 +00:00
Keno Fischer
b2b7911686 Fix cross-endianness RuntimeDyld relocation for ARM
rL284780 fixed the PREL31 relocation and added a test for it. Being
the first such test for ARM relocations, it exposed incorrect endianness
assumptions (causing buildbot failures on big-endian hosts). Fix that by
using the same helpers used for the x86 case.

llvm-svn: 284789
2016-10-20 22:15:56 +00:00
Li Huang
0a4f3b84af [SCEV] Add a threshold to restrict number of mul operands to be inlined into SCEV
This is to avoid inlining too many multiplication operands into a SCEV, which could 
take exponential time in the worst case.

Reviewers: Sanjoy Das, Mehdi Amini, Michael Zolotukhin

Differential Revision: https://reviews.llvm.org/D25794

llvm-svn: 284784
2016-10-20 21:38:39 +00:00
Keno Fischer
df5354029f Fix PREL31 relocation on ARM
Summary:
This is a 31bits relative relocation instead of a 32bits absolute relocation.

Reviewers: t.p.northover, peter.smith, rengolin

Subscribers: aemerson, llvm-commits, samparker

Differential Revision: https://reviews.llvm.org/D25069

llvm-svn: 284780
2016-10-20 21:15:29 +00:00
Michael Kuperstein
ae8887d98b [X86] Enable interleaved memory access by default
This lets the loop vectorizer generate interleaved memory accesses on x86.

Differential Revision: https://reviews.llvm.org/D25350

llvm-svn: 284779
2016-10-20 21:04:31 +00:00
Daniel Berlin
aabe0b98f9 [MSSA] Avoid unnecessary use walks when calling getClobberingMemoryAccess
Summary:
This allows us to mark when uses have been optimized.
This lets us avoid rewalking (IE when people call getClobberingAccess on everything), and also
enables us to later relax the requirement of use optimization during updates with less cost.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25172

llvm-svn: 284771
2016-10-20 20:13:45 +00:00