Evan Cheng
3ec2e08a37
Allow the target to override the ISD::CondCode that's to be used to test the
...
result of the comparison libcall against zero.
llvm-svn: 33701
2007-01-31 09:29:11 +00:00
Nate Begeman
dc46021355
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
Anton Korobeynikov
611d5e2eda
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
Reid Spencer
4fe8454735
Don't #include DerivedTypes.h in this header. Make adjustments to
...
compensate. Move a function out of line to TargetLowering.cpp
llvm-svn: 33153
2007-01-12 23:21:42 +00:00
Evan Cheng
a8ed507f15
- Move RTLIB::Libcall enum to a separate file.
...
- Code clean up.
llvm-svn: 33148
2007-01-12 22:49:32 +00:00
Evan Cheng
3e3e3865b8
Silence a bogus compiler warning.
...
llvm-svn: 33145
2007-01-12 22:30:07 +00:00
Reid Spencer
373d2bccea
For PR1064:
...
Implement the arbitrary bit-width integer feature. The feature allows
integers of any bitwidth (up to 64) to be defined instead of just 1, 8,
16, 32, and 64 bit integers.
This change does several things:
1. Introduces a new Derived Type, IntegerType, to represent the number of
bits in an integer. The Type classes SubclassData field is used to
store the number of bits. This allows 2^23 bits in an integer type.
2. Removes the five integer Type::TypeID values for the 1, 8, 16, 32 and
64-bit integers. These are replaced with just IntegerType which is not
a primitive any more.
3. Adjust the rest of LLVM to account for this change.
Note that while this incremental change lays the foundation for arbitrary
bit-width integers, LLVM has not yet been converted to actually deal with
them in any significant way. Most optimization passes, for example, will
still only deal with the byte-width integer types. Future increments
will rectify this situation.
llvm-svn: 33113
2007-01-12 07:05:14 +00:00
Evan Cheng
032a597692
Store default libgcc routine names and allow them to be redefined by target.
...
llvm-svn: 33105
2007-01-12 02:11:51 +00:00
Reid Spencer
f3265181e2
Rename BoolTy as Int1Ty. Patch by Sheng Zhou.
...
llvm-svn: 33076
2007-01-11 18:21:29 +00:00
Evan Cheng
38cb858ee5
- Remove isSetCCExpensive() etc. These are no longer used.
...
- Add isSelectExpensive() etc. It's used to tell codegen that select is expensive for a given target, avoid using it if possible. Currently it's only
used to expand FCOPYSIGN.
llvm-svn: 32939
2007-01-05 23:31:08 +00:00
Reid Spencer
a7eaf62ace
For PR950:
...
Change integer type names for signless integer types
llvm-svn: 32777
2006-12-31 05:23:18 +00:00
Evan Cheng
7684d815d1
Add getTypeToExpandTo() which recursively walks TransformToType to determine
...
the intrinsic type to expand to.
llvm-svn: 32558
2006-12-13 20:52:00 +00:00
Evan Cheng
2346bdd8c3
Update comments.
...
llvm-svn: 32532
2006-12-13 06:12:35 +00:00
Evan Cheng
5c6304ca6e
Update comments.
...
llvm-svn: 32531
2006-12-13 06:09:03 +00:00
Anton Korobeynikov
e76b69846d
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
Evan Cheng
c050bb298f
Add a mechanism to specify whether a target supports a particular indexed load / store.
...
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
Evan Cheng
89ee587963
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
Evan Cheng
6b7d127df9
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
...
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
Evan Cheng
db0add3bcb
Added target hook for post-indexed memory ops transformation.
...
llvm-svn: 31499
2006-11-07 09:04:16 +00:00
Evan Cheng
466e20fca2
Rename
...
llvm-svn: 31413
2006-11-03 07:21:16 +00:00
Evan Cheng
9ebbced355
Added a target specific hook to check whether / how a node can be transformed
...
into a pair of base / offset nodes for pre-indexed load / store ops.
llvm-svn: 31407
2006-11-03 03:04:06 +00:00
Chris Lattner
4cb79a5f9d
generalize this api
...
llvm-svn: 31365
2006-11-02 01:39:10 +00:00
Chris Lattner
d9afd310a6
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
Evan Cheng
fe5bb5dbe6
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Evan Cheng
967d6af1d2
Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes.
...
Chain and address ptr remains as operands. SrcValue, extending mode, extending
VT (or rather loaded VT before extension) are now instance variables of
LoadSDNode.
Introduce load / store addressing modes to represent pre- and post-indexed
load and store. Also added an additional operand offset that is only used in
post-indexed mode (i.e. base ptr += offset after load/store).
Added alignment info (not yet used) and isVolatile fields.
llvm-svn: 30843
2006-10-09 20:55:20 +00:00
Chris Lattner
77545e4a28
Add support for targets to declare that they use a GOT
...
llvm-svn: 30777
2006-10-06 22:46:34 +00:00
Evan Cheng
494e8e6971
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
Duraid Madina
51396ffd3e
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
Andrew Lenharth
a2bda5b0e1
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
Reid Spencer
574d4e6992
For PR786:
...
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.
llvm-svn: 28453
2006-05-24 19:21:13 +00:00
Evan Cheng
89f7ea0382
Another typo. Pointed out by Nate Begeman.
...
llvm-svn: 28353
2006-05-17 18:22:14 +00:00
Evan Cheng
09c4a5d032
Fix a mis-leading comment.
...
llvm-svn: 28350
2006-05-17 18:08:20 +00:00
Chris Lattner
3e13a7d49e
There is now a default impl of this method
...
llvm-svn: 28336
2006-05-16 22:52:11 +00:00
Andrew Lenharth
14504c85ed
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
Chris Lattner
06d617846d
Add some new methods for computing sign bit information.
...
llvm-svn: 28144
2006-05-06 09:26:22 +00:00
Owen Anderson
71bc529dfa
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Evan Cheng
ec4d1668ef
Added a virtual method isVectorClearMaskLegal to TLI. It is similar to
...
isShuffleMaskLegal, used to determine if it makes sense to turn a
"vector clear" (e.g. pand V, <0, -1, 0, -1> to a shuffle of the vector and
a zero vector.
llvm-svn: 27873
2006-04-20 08:54:13 +00:00
Chris Lattner
048bc55352
Provide a default impl of LowerArguments
...
llvm-svn: 27605
2006-04-12 16:21:12 +00:00
Chris Lattner
1dc3c03ee7
Move isShuffleLegal from TLI to Legalize.
...
llvm-svn: 27398
2006-04-04 17:21:22 +00:00
Chris Lattner
9925c6018f
Allow targets to have fine grained control over which types various ops get
...
promoted to, if they desire.
llvm-svn: 27389
2006-04-04 00:25:10 +00:00
Chris Lattner
8e0dfe133c
Modify the TargetLowering::getPackedTypeBreakdown method to also return the
...
unpromoted element type.
llvm-svn: 27273
2006-03-31 00:46:36 +00:00
Chris Lattner
557951b354
Add a method useful for decimating vectors.
...
llvm-svn: 27269
2006-03-31 00:28:23 +00:00
Evan Cheng
54215cd1ea
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
...
64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
Chris Lattner
a3663c3dbb
Add some helper methods
...
llvm-svn: 26882
2006-03-20 00:55:52 +00:00
Evan Cheng
cad75d9f0c
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
Evan Cheng
ed013bd937
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
Chris Lattner
c656f75535
custom lowered nodes are legal too
...
llvm-svn: 26561
2006-03-05 23:49:19 +00:00
Evan Cheng
0c445855f2
Number of NodeTypes now exceeds 128.
...
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
Chris Lattner
40501a50fe
Add interfaces for targets to provide target-specific dag combiner optimizations.
...
llvm-svn: 26442
2006-03-01 04:52:55 +00:00
Evan Cheng
b8a44ab1dd
Missing a cast previously.
...
llvm-svn: 26434
2006-03-01 00:58:54 +00:00
Chris Lattner
0957a2e87c
Add C_Memory operand type
...
llvm-svn: 26344
2006-02-24 01:10:14 +00:00
Chris Lattner
ed45ad33b7
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
...
Patch by Martin Partel!
llvm-svn: 26313
2006-02-22 16:23:43 +00:00
Chris Lattner
6bb2c3e9cd
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner
ed3b59056a
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
...
select different sets of registers depending on the type requested.
llvm-svn: 26304
2006-02-21 23:10:29 +00:00
Nate Begeman
aef186befc
Fix a nit sabre noticed
...
llvm-svn: 26262
2006-02-17 18:06:19 +00:00
Nate Begeman
0bc71999b9
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
Evan Cheng
f6c74c0096
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
Chris Lattner
478eb50b79
getConstraintType should be virtual.
...
llvm-svn: 26041
2006-02-07 20:13:44 +00:00
Chris Lattner
2395722dbd
Add some methods for inline asm support.
...
llvm-svn: 25950
2006-02-04 02:12:09 +00:00
Nate Begeman
2d9838ec9b
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
Chris Lattner
5583b2e227
Clear the OpAction field before setting it. This allows a target to set
...
an instruction operation action to Expand, then set it to Legal later.
llvm-svn: 25812
2006-01-30 06:09:03 +00:00
Chris Lattner
a1cc69e24e
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,
...
making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.
llvm-svn: 25802
2006-01-30 04:08:18 +00:00
Chris Lattner
7f64ff5ce0
Pass the address of the main MaskedValueIsZero function to allow recursion.
...
llvm-svn: 25797
2006-01-30 03:48:36 +00:00
Chris Lattner
a8ca8f5eb9
Clean up the interface to ValueTypeActions, allowing Legalize to use a copy
...
of it more cleanly. Double the size of OpActions, allowing it to hold actions
for any VT.
llvm-svn: 25782
2006-01-29 08:40:37 +00:00
Chris Lattner
2240c0df71
remove this method I just added, now is not the time.
...
llvm-svn: 25729
2006-01-28 03:43:33 +00:00
Chris Lattner
063c13029b
add a new callback
...
llvm-svn: 25727
2006-01-28 03:37:03 +00:00
Nate Begeman
87c2c0e66b
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
Nate Begeman
d2c6fbef4a
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Chris Lattner
ab8e0e40f9
Add a method for inline asm support.
...
llvm-svn: 25656
2006-01-26 20:27:33 +00:00
Nate Begeman
c29fac7fce
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
f4b53efbb2
Add a enum to specify target scheduling preference: SchedulingForLatency or
...
SchedulingForRegPressure. Added corresponding methods to set / get the value.
llvm-svn: 25598
2006-01-25 09:09:02 +00:00
Chris Lattner
8fe9dd16fb
Provide an interface for Targets to specify their stack pointer register
...
for llvm.stacksave/restore.
llvm-svn: 25275
2006-01-13 17:47:52 +00:00
Jeff Cohen
8727139340
Oh oh... Unix is case sensitive.
...
llvm-svn: 24928
2005-12-22 01:46:59 +00:00
Jeff Cohen
8afabfd8f1
Make it compile with VC++.
...
llvm-svn: 24927
2005-12-22 01:44:51 +00:00
Evan Cheng
822f360f84
Added TargetLowering::isMaskedValueZeroForTargetNode() declaration.
...
llvm-svn: 24923
2005-12-21 23:15:41 +00:00
Evan Cheng
44e4e6a57f
Added a hook to print out names of target specific DAG nodes.
...
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Nate Begeman
a1c2df2471
Add the majority of the vector machien value types we expect to support,
...
and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
Nate Begeman
5784fb4adf
Teach the type lowering code about turning packed types into vector types.
...
Next step: generating vector dag nodes, and legalizing them into scalar
code.
llvm-svn: 24404
2005-11-17 21:44:42 +00:00
Nate Begeman
6c42f509bc
Invert the TargetLowering flag that controls divide by consant expansion.
...
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00
Nate Begeman
2b0b27775d
Enable targets to say that integer divide is expensive, which will trigger
...
an upcoming optimization in the DAG Combiner.
llvm-svn: 23834
2005-10-20 02:14:14 +00:00
Nate Begeman
ee581735d9
Add the ability to lower return instructions to TargetLowering. This
...
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
Chris Lattner
62922d5727
Add a new flag for targets where setjmp/longjmp saves/restores the signal mask,
...
and _setjmp/_longjmp should be used instead (for llvm.setjmp/llvm.longjmp).
llvm-svn: 23479
2005-09-27 22:13:36 +00:00
Reid Spencer
31b20389f9
Change the names of member variables per Chris' instructions, and document
...
them more clearly.
llvm-svn: 23118
2005-08-27 19:09:02 +00:00
Chris Lattner
e91069c4de
add some forward defs
...
llvm-svn: 23100
2005-08-26 21:06:40 +00:00
Chris Lattner
ac19224b29
spell this right!
...
llvm-svn: 23097
2005-08-26 20:53:44 +00:00
Chris Lattner
98bd9339ce
Add a hook
...
llvm-svn: 23096
2005-08-26 20:53:09 +00:00
Chris Lattner
b71b78a79d
rename hasNativeSupportFor* -> is(Operation|Type)Legal.
...
llvm-svn: 23011
2005-08-24 16:34:59 +00:00
Jeff Cohen
81980781a1
Eliminate tabs and trailing spaces.
...
llvm-svn: 22520
2005-07-27 05:53:44 +00:00
Reid Spencer
40c5ebe4eb
For: memory operations -> stores
...
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.
llvm-svn: 22468
2005-07-19 04:52:44 +00:00
Chris Lattner
bf100c8bdb
Make several cleanups to Andrews varargs change:
...
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
llvm-svn: 22338
2005-07-05 19:57:53 +00:00
Andrew Lenharth
108f509fb5
header file changes for varargs
...
llvm-svn: 22253
2005-06-18 18:31:30 +00:00
Chris Lattner
ae59fdbd99
Pass the dag into LowerOperation
...
llvm-svn: 22005
2005-05-14 05:51:05 +00:00
Chris Lattner
9d788e93a6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
Chris Lattner
ccb86c9acc
LowerCallTo now takes the cc to use
...
llvm-svn: 21901
2005-05-12 19:57:08 +00:00
Chris Lattner
045b3f0110
Add a little hook
...
llvm-svn: 21883
2005-05-12 02:02:21 +00:00
Misha Brukman
58c97e67f3
Remove trailing whitespace
...
llvm-svn: 21412
2005-04-21 20:59:05 +00:00
Chris Lattner
f275f2af41
Allow targets which produce setcc results in non-MVT::i1 registers to describe
...
what the contents of the top bits of these registers are, in the common cases
of targets that sign and zero extend the results.
llvm-svn: 21145
2005-04-07 19:41:18 +00:00
Nate Begeman
e0ab2218d1
Change LowerCallTo to take a boolean isVarArg argument. This is needed
...
by the PowerPC backend, and probably others in the future.
llvm-svn: 20843
2005-03-26 01:30:30 +00:00
Chris Lattner
4938a7c8a1
Move all data members to the end of the class.
...
Add a hook to find out how the target handles shift amounts that are out of
range. Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).
This defaults to undefined, which is conservatively correct.
llvm-svn: 19676
2005-01-19 03:36:03 +00:00
Chris Lattner
8dd332e4e5
Add comments
...
Add fields to hold the result type of setcc operations and shift amounts.
llvm-svn: 19618
2005-01-16 23:59:30 +00:00
Chris Lattner
e38f72316d
Revamp supported ops. Instead of just being supported or not, we now keep
...
track of how to deal with it, and provide the target with a hook that they
can use to legalize arbitrary operations in arbitrary ways.
llvm-svn: 19609
2005-01-16 07:27:49 +00:00
Chris Lattner
1d0e1ffe02
Move some information out of LegalizeDAG into the generic Target interface.
...
llvm-svn: 19581
2005-01-16 01:10:58 +00:00
Chris Lattner
42dd85fc56
Add interfaces to lower varargs and return/frame address intrinsics.
...
llvm-svn: 19406
2005-01-09 00:00:31 +00:00
Chris Lattner
2a75da3851
Make LowerCallTo more generic and useful.
...
llvm-svn: 19373
2005-01-08 19:25:39 +00:00
Chris Lattner
01ed041b94
First draft of a new Target interface
...
llvm-svn: 19323
2005-01-07 07:44:22 +00:00